lecture6

lecture6 - CMOS VLSI For Computer Engineering Lecture 5...

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CMOS VLSI For Computer Engineering Lecture 5 – Power Prof. Luke Theogarajan parts adapted form Harris – www.cmosvlsi.com and Rabaey- http://bwrc.eecs.berkeley.edu/icbook/sli des.htm
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CMOS VLSI for Computer Engineering 7: Power 2 Outline Power and Energy Dynamic Power Static Power
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CMOS VLSI for Computer Engineering 7: Power 3 Power and Energy Power is drawn from a voltage source attached to the V DD pin(s) of a chip. Instantaneous Power: Energy: Average Power: ( ) ( ) ( ) P t I t V t = 0 ( ) T E P t dt = avg 0 1 ( ) T E P P t dt T T = =
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CMOS VLSI for Computer Engineering 7: Power 4 Power in Circuit Elements ( 29 ( 29 VDD DD DD P t I t V = ( 29 ( 29 ( 29 2 2 R R R V t P t I t R R = = ( 29 ( 29 ( 29 ( 29 0 0 2 1 2 0 C C V C dV E I t V t dt C V t dt dt C V t dV CV = = = =
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CMOS VLSI for Computer Engineering 7: Power 5 Charging a Capacitor When the gate output rises Energy stored in capacitor is But energy drawn from the supply is Half the energy from V DD is dissipated in the pMOS transistor as heat, other half stored in capacitor When the gate output falls Energy in capacitor is dumped to GND Dissipated as heat in the nMOS transistor 2 1 2 C L DD E C V = ( 29 0 0 2 0 DD VDD DD L DD V L DD L DD dV E I t V dt C V dt dt C V dV C V = = = =
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CMOS VLSI for Computer Engineering 7: Power 6 Switching Waveforms Example: V DD = 1.0 V, C L = 150 fF, f = 1 GHz
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CMOS VLSI for Computer Engineering 7: Power 7 Switching Power [ ] switching 0 0 sw 2 sw 1 ( ) ( ) T DD DD T DD DD DD DD DD P i t V dt T V i t dt T V Tf CV T CV f = = = = C f sw i DD (t) VDD
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CMOS VLSI for Computer Engineering 7: Power 8 Activity Factor Suppose the system clock frequency = f Let f sw = α f, where α = activity factor If the signal is a clock, α = 1 If the signal switches once per cycle, α = ½ Dynamic power: 2 switching DD P CV f α =
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7: Power 9 Short Circuit Current When transistors switch, both nMOS and pMOS networks may be momentarily ON at once Leads to a blip of “short circuit” current. < 10% of dynamic power if rise/fall times are
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This note was uploaded on 01/16/2012 for the course ECE 223 taught by Professor Luketheogarajan during the Fall '11 term at UCSB.

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lecture6 - CMOS VLSI For Computer Engineering Lecture 5...

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