SolutionsFinal2009

SolutionsFinal2009 - UNIVERSITY OF CALIFORNIA, SANTA...

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Unformatted text preview: UNIVERSITY OF CALIFORNIA, SANTA BARBARA DEPARTMENT OF ELEUI‘RIUAL & COMPUTER ENGINEERING CMOS VLSI FOR COMPUTER ENGINEERING 19/1BB/594BB PROFESSOR, THEOGARAJAN FINAL EXAM, DECEMBER 4, 2009 ' O Name: 5 LuTioMS This is open book and open notes exam. For all questions make reasonable approximations. Unless otherwise specified ignore body effect. All necessary formulas and values are given at the end of the exam for your cOnvenience. GOOD LUCK! Fewer the questions in the spaces provided on the question sheets. If you run out of room for an answer, continue on the back of the page. Points 3 ECE 194BB / 594E313 Final Exam December 4, 2009 Question 1: 45points Consider the circuit shown in figure 1 which is a clock generator block used to double the Clock frequency in the Pentium 4 micrOprocessor. Output Clock Input clock Figure 1: Question 1 (a) (7 points) How does the circuit double the Clock frequqency? The circuit 7:, Gimme, edge, rim-er:ch “5.9. T1; genena‘res CL :10th 3:)"err Signed. On bO'Ch The rising edge, and fi.\iin& edge 0F 1he anming (Heck. Since The C‘trcuu; confirms ox Bel¥~Tevm1ncning precnarge “Le. Wm WM Wm Pun mgh af'Wr' Qpbrwimaiqtfi '53 Tnv dams: C 2 Tm: 1- Pun-amp) each edge oé’ rm clod< win generate we pulses 'be evena clock. the circmt, (Mame-e, Th9. "incoming. 'fi‘eq, EOE 1941313 / 594BB Final Exam (Continued) December 4, 2009 (b) (8 points) Can you draw a logic—gate level version of this circuit? or QED—«r» Page 2 0f 21 ECE 194BB/594BB Final Exam (Continued) December 4; 2009 (e) (10 points) Size the original circuit such that it can drive a 20pF load. The output clock has to have a pulse width of 180138 and the input clock frequency is 1.2GHz. Given ReqTL = 2.69kflpm, Reqp = 6.511691er; Cdn 4— 2.3fF/mn, Gym -- 1.5fFfpam, Cd!) : 2.3fF/um and 093? = 1.5 f F/ um. Make reasonable assmnptions about rise and fall times. Vdd ,__._ duet-*6 - Tr ~ \0‘70 04? «Maps = 4L6?!»- Tg w \Oo/O 0‘?“st 7— 4’th5' 0—— Soolo T- 41 .596 = 31315393: 60.28%. __E “a .e l Peqn Q Pg 1: -—-_.._ :- efl- = ‘-—-——-—--eqff an - 1‘36“: 9 Peqp 2 "tpb 2 = z‘chbe- “1.36951 “kid: 909$ '—' '21.” 8. ‘tdI'tpo C9140 P t? a 3* A) on u m 4.. l7 L._J <1 M? Z\ 5 h , “5‘ 3.98 a h=4‘q'2.' J Co? STD dom‘ma c4105??— Page 3 of 21 EOE 194BB/ 594813 Final Exam (Continued) contd. .. Pun atom: (oops. Pull. up = 6095. c: 410pr 1- (Oq: x-an‘j 25% Arm 6 5:, Re OP H33— (‘EObPF "r (mp-firmn) 2.3K) P Mm 6095: 22am W (41060? 1- CQPY2%)Q~§::} 4-17 mm = [Ce-Hon r u —- . 5 I 3 a can @095 .. 21.84 m pm ~r Q0 1;?“ “an a can ‘20.?Jps: 2‘34. ns- Arm Mn: |I one x [03mm ENM tpu=2tp3 In: 2.Sb_ p .11 T3 = 3144- h= Sub December 4, 2009 Page 4 of 21 ECE 194BB/594BB Final Exam (Continued) December 4, 2009 (d) ( 10 points) Size your static circuit such that it can drive a EUpF load. The output clock has to have a pulse Width of 180m and the input clock frequency is 1. EGHZ. 5.7.5 PF R3,: Z—NRNO 3mg: list“ (16% 0-? -cm dram, be 9’..- 18095.. D: "CPOCP‘r 5.3.3. P ‘30: '2‘ (4+ 2 lb 3% ) $5“ = W 2 ’q‘? :1. 2 (450)”. .3. _ n _:f It, _ acts H: 4‘3q5. _—__'___w_—_—_—w_—_—_I——mw Page 5 of 21 ECE 19/1813/ 594BB Final Exam (Continued) December 4, 2009 contd. .. mm Page 6 0f 21 EOE 1941313 / 5941313 Final Exam (Continued) December 4, 2009 (e) (10 points) Graduate Students only: Calculate the power consumption for both the static and dynamic versions of the circuit. C) :.:. d CL V461 Ox: 2 L 4 Tran‘3\‘tion /C\oac) P: h‘ZGHEA CL: 209‘: *- [Zmnfi-LOP) Came +931 C8 TWCQ. amzlortér 6?:( 312m U verslun. EOE 1 9438/ 594138 Final Exeun (Continued) December 4, 2009 centd... Page 8 of 21 ECE 1941313 / 5941313 Final Exam (Continued) December 4, 2009 2. Question 2: lOpoints One method to save area is to employ dynamic phase 2 latches in a latch pipelined system, shown in figure 2. Answer the following questions Clk Figure 2: Question 2 (a) (5 points) Given that Vdd = 1.8V Calculate the lowest clock frequency you can use so that the dynamic node barely discharges i.e. < lOOnV while driving a mini— mum sized inverter. Ioffn : 94pA/nm, Jeff” : 25.2pA/nm, RegsL = 2.69k9nm, Reg}, : 6.51kflpm, Cam = 2.3fF/nm, Cyan : 1.5fF/nm, Cd], : 2.3fF/nm, 093p 21.5fF/nm and ,6 z 2.5. '1 o¢~¢n 7 lump «‘ : Céfi (M‘ 30 net Cwn’evxx dl'éfikflu’e‘nn'g ‘Tliu. mach). CW: loo y‘d act—232 =2 §_.__EPA‘ \ nan. N 7* 65PA' 02'1'; [8.3593 sense": Ii = . N“ (0.2"; pm) dr It)va assq: :tmes— ‘1- h2<LH1 l.___-'"'_—— Sue cap Pub-b am (My; ' . q; __ q QT " DiCaq'lD = @MHE = Sésnfi-g. I 26595:. W Page 9 of 21 EOE 194BB/594BB Final Exam (Continued) December 4, 2009 (b) (5 points) HOW can you ensure that the dynamic latch works at all frequencies? L359 0 Puxned God? SW3 TM- puxse ham-eh 'r-s Tndepeqdmr DEL the C1008 Hequenuax The d1$CharQ€ TIM cam be LO‘H'lrolAeA, Page 10 0f 21 EOE 194BB / 5941313 Final Exam (Continued) December 4, 2009 3. Question 3: 45points You are given the task to design a word-line decoder for 16K X 64 bit memory arranged as 1024 rows by 1024 bits as shown in figure 3 1024bits Wotdline 75 1024mm Row Decoder Coiumn Decoder 8: MUX Read/Write l/O Figure 3: Circuit for Question 3 m+n Address (a) (2 points) What are the values of In and n shown in figure? Zh=koz¢ mac, 2‘“: mzq‘. W Page 11 of 21 EOE 194BB/594BB Final Exam (Continued) December 4, 2009 (b) (3 points) Given that the wordh'ne is routed horizontally in MetalQ with a capac— itance of 0.22fF/pm and the gate capacitance is 09m = 1.5fF/hm What is the total lumped load seen by the wordline driver? L; = h6p_w_\ -1o‘2<$, 'ou-s = I536 mm. bu: Chine: 0.22“: W Page 12 0f 21 ECE 1941313 / 594BB Final Exam (Continued) DoCember 4, 2009 (c) (10 points) Find the total path efiort in the row address decode path the maximum load any input gate can offer is SfF. Make sure you t and logical effort into account. Assume that both bit input. asmiming that aka the branching and 52'? are available at the row (wooden =lomts. EFL'Zi = QQ. '2. 10 bit decoder USlna Mme; 2 T/(c gates E- Srages balk-2F $67.. H: strata ‘0“ Stages ~—~—3 aqaw (gr—"5161. GBH = MODS 110‘? -1 EGBH = '12 (‘Fox G-om {aptlum 65¢). Page 13 of 21 EOE 194138 /594BB Final Exam (Continued) December 4, 2009 contdm Wm ECE 194133 / 5948.8 Final Exam (Continued) December 4, 2009 (d) (10 points) Given that you are usng static gates to implement this design and the Wire resistance is (1169/ am what is the delay from the time the clock rises and the address is presented to the decoder to the wm'dline going high. Given that the delay of a FO—4 inverter is 7-5ps and "y : 1.5, Assume that both bit and 3% are available at the input. Tong. data given io—avages :5 R: hS'BErvxm. D.{bSI_ 2 245.065L tPD ( P+ 8%) +0.6QQQ/ ‘7 Cw weave ‘tpg: 75 Go I 38 1'“ ZO-‘ffips. ‘71—: QQQPF +_‘. 1.5 O'EQRQ= ten-(1‘91. . "ford porch Gimme: QS6P5_ Page 15 of 21 ECE 194BB / 5941313 Final Exam (Continued) December 4, 2009 contd. .. m Page 16 of 21 EOE 194BB/594BB Final Exam (Continued) December 4, 2009 (e) (10 points) Given that you are using domino gates to implement this design and the wire resistance is 0.16Q/pm What is the optimal delay from the input address to the wordiine going high. Assume that both bit and are available at the input NOTE: The input address latch is the first stage of the domino with. RC delog Stags 1N; sam_ ThPu-w address. {ox Ch '90::th branch 10:3:K 1 a 13 3 2/5 5/6 94: ya Bu: ‘Is 5/6 V3 3/6 p l 5/ _ 6 Fl P=573 2/5 5/2, 1/3 576 EPA —. l-r 5/6+ 213/51- 6:1-‘5 ~L i. i "3‘13bu 3 fig g/e zooms B=5l2 _ 1.Q‘3°F H 5421'— :5‘19’ 66H : 2838. .51 ‘?=2fl D= tpoCP+ ml ): 2045 (ES +8203 = 615.5493 *W EOE 1941313 / 594BB Final Exam (Continued) December 4, 2009 contd. .. Page 18 of 21 194BB/ 5941313 Final Exam (Continued) December 4, 2009 (f) (10 points) Graduate Students only: Size the preehaxge tree to ensure no preeharge race occurs assuming a footlese domino implementation. Page 19 of 21 EOE 194BB/594BB Final Exam (Continued) December 43 2009 contd. .. W Page 20 of 21 EOE 194BB/594BB Final Exam (Continued) December 117 2000 For all problems, we are using the 0.18pm technology node. The maximum supply voltage for this technology is VifiMa-x) : 1.8 V For hand calculation you may use the following parameters NMOS: Vt" : 0.5V, Usat : 1.6 X 105Trt/3,t0m : 41 X 10407713133“ 2 6 X 104V/cm, CW; : 8.57fF/a21 ,u : 412cm2/V w s Regn I 2.69kQ/am PMOS: 14p 2 —0.5V,vsat : 1.0 x 105m/s,tm : 41 x 10"10m, Em : 24 X 104V/cm, CW 2 8.57fF/p2,,a : 83cm2/V — 8 Reg? = 6.51kQ/pm You may find the following equations useful V H £VGSfiWJE5utL Dssat i (VGS—%)+EsatI—‘ Ida-n = no”? (V95 — v; — as) Va 7 := 1.5 for this process For an inverter chain containing N inverters: tam : a (1 + g) f = V? For a logic path containing N logic gates: tlogicgate : t130 (p + G = Hiflvgi B : Htivbz' . i MM bl — Can—path t F = 1133915: H = GBF h:W Page 21 0f 21 ...
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This note was uploaded on 01/16/2012 for the course ECE 223 taught by Professor Luketheogarajan during the Fall '11 term at UCSB.

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SolutionsFinal2009 - UNIVERSITY OF CALIFORNIA, SANTA...

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