This preview has intentionally blurred sections. Sign up to view the full version.
View Full Document
Unformatted text preview: me. As long as the propagation medium does not disperse the pulses too badly, they can lie recovered at a receiver. Similarly, if a VLSI system has low dispersion, i.e., nearly equal
bontamination and propagation delays, it can send more than one wave of data without Explicit latching. Such wave pipelining offers the potential of high throughput and low
pquencing overhead. However, it is difﬁcult to perform in practice because of the variabil— b' of data delay. [se the timing parameters in Table 10.5 for the following exercises.
l IIBLE 10.5 Sequencing element parameters Ill1042.0 . ‘_'. “cantamin'atignl’
' ' " Dela! *1 For each of the following sequencing styles,
tion delay available Within a 500 ps clock
no time borrowing takes place. a) Flip—ﬂops b) Two—phase transparent latches
c) Pulsed latches with 80 ps pulse width Repeat Exercise 10.1 if the clock skew between any two elements can be up to 50 ps.
For each of the following sequencing styles, determine the minimum logic contami— nation delay in each clock cycle (or halfcycle, for twophase latches). Assume there
is zero clock skew. a) Flip—ﬂops
b) Two—phase transparent latches with 50% duty cycle clocks c) Tweephase transparent latches with 60 ps ofnonoverlap between phases
(1) Pulsed latches with 80 ps pulse width Repeat Exercise 10.3 if the clock skew between any two elements can be up to 50 ps. Exercises m Chapter 10 Sequential Circuit Design 10.5 Suppose one cycle of logic is particularly critical and the next cycle is nearly  n___.
Determine the maximum amount of time the ﬁrst cycle can borrow into the my end for each of the following sequencing styles. Assume there is zero clock saw,
and that the cycle time is 500 ps. a) Flip—ﬂops
b) Two~phase transparent latches with 50% duty cycle clocks c) Two—phase transparent latches with 60 ps of nonoverlap between phases
d) Pulsed latches with 80 ps pulse Width 10.6 Repeat Exercise 10.5 if the clock skew between any two elements can be up to I.
ps.
10.7 Prove EQ_(10.17). 10.8 Consider a ﬂip—ﬂop built from a pair of transparent latches using nonovetlap It; clocks. Express the setup time, hold time, and clock—to— Q delay of the ﬂip—ﬂop terms of the latch timing parameters and rmonovcﬂap, relative to the rising edge .;_S
4’1 10.9 For the path in Figure 10.54, determine which latches borrow time and if any '
setup time Violations occur. Repeat for cycle times of 1200, 1000, and 800 p5. Assume there is zero clock skew and that the latch delays are accounted for in :35
propagation delay a) A1 = 550 ps; A2 = 580 ps; A3 = 450 ps; A4 : 200 135
13) A1 : 300 ps; A2, = 600 ps; A3 : 400 ps; A4 = 550 ps elk elk elk elk
  FIGURE 10.54 Example path elk ' Latch 1
Latch 2 10.10 Determine the minimum clock period at which the circuit in Figure 10.55 will 1
operate correctly for each of the following logic delays. Assume there is zero cl i;
skew and that the latch delays are accounted for in the propagation delay a) A1 = 300 ps; A2 : 400 ps; A3 = 200 ps; A4 2 350 ps
1)) A1 = 300 ps; A2 = 400 ps; A3 : 400 ps; A4 = 550 ps
c) A1 = 300 ps; A2 = 900 ps; A3 = 200 ps; A4 = 350 ps ‘URE _1 0.55 Another example path Repeat Exercise 10.10 if the clock skew is 100 ps. Label the timing types of each signal in the circuit from Figure 10.54. The ﬂip
ﬂop is constructed with back—to—back transparent latchesithe ﬁrst controlled by
CALI) and the second by 611%. Using a simulator, compare the DetOeQ propagation delays of a conventional dynamic latch from Figure 10.17(d) and aTSPC latch from Section 10.3.11.
Assume each latch is loaded with a fanout of 4. Use 4 zl—Wide clocked transistors
and tune the other transistor sizes for least propagation delay. Using a simulator, ﬁnd the setup and hold times of aTSPC latch under the
assumptions of Exercise 10.13. Determine the maximum logic propagation delay available in a cycle for a tradie
tional domino pipeline using a 500 ps clock cycle. Assume there is zero clock skew. Repeat Exercise 10.15 if the clock skew between any two elements can reach 50 ps. Determine the maximum logic propagation delay available in a cycle for a four—
phase skew—tolerant domino pipeline using a 500 ps clock cycle. Assume there is
zero clock skew. Repeat Exercise 10.17 if the clock skew between any two elements can be up to 50
ps. How much time can one phase borrow into the next in Exercise 10.18 if the clocks
each have'a 50% duty cycle? Assume fhold = 0. Repeat Exercise 10.18 if the clocks have a 65% duty cycle. Design a fast pulsed latch. Make the gate capacitance on the clock and data inputs
equal. Let the latch drive an output load of four identical latches. Simulate your
latch and ﬁnd the setup and hold times and clock—to~Q propagation and contami~
nation delays. Express your results in F04 inverter delays. Simulate the worst—case propagation delay of an Swinput dynamic NOR gate driv—
ing a fanout of 4. Report the delay in all 16 design corners (voltage, temperature,
nMOS, pMOS). Also determine the delay of a fanout—of—4 inverter in each of
these corners. By what percentage does the absolute propagation delay of the NOR
gate vary across corners? By What percentage does its normalized delay vary (in
terms of F04 inverters)? Comment on the implications for circuits using matched
delays. Exercises m ...
View
Full Document
 Fall '11
 LukeTheogarajan

Click to edit the document details