lecture9_PLL_DLL

lecture9_PLL_DLL - CMOS VLSI For Computer Engineering...

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CMOS VLSI For Computer Engineering Lecture 8: Clock Distribution, Parts adapted from http://www3.hmc.edu/~harris/cmosvlsi/ 4e/index.html
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CMOS VLSI for Computer Engineering 2 Clock Distribution On a small chip, the clock distribution network is just a wire And possibly an inverter for clkb On practical chips, the RC delay of the wire resistance and gate load is very long Variations in this delay cause clock to get to different elements at different times This is called clock skew Most chips use repeaters to buffer the clock and equalize the delay Reduces but doesn’t eliminate skew
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CMOS VLSI for Computer Engineering 3 Example Skew comes from differences in gate and wire delay With right buffer sizing, clk 1 and clk 2 could ideally arrive at the same time. But power supply noise changes buffer delays clk 2 and clk 3 will always see RC skew 3 mm 1.3 pF 3.1 mm gclk clk 1 0.5 mm clk 2 clk 3 0.4 pF 0.4 pF
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CMOS VLSI for Computer Engineering 4 Review: Skew Impact F1 F2 clk clk clk Combinational Logic T c Q1 D2 Q1 D2 t skew CL Q1 D2 clk Q1 clk D2 clk t skew t setup t pcq t pdq t cd t hold t ccq ( 29 setup skew sequencing overhead hold skew pd c pcq cd ccq t T t t t t t t t - + + - + 1 4 442 4 4 43 Ideally full cycle is available for work Skew adds sequencing overhead Increases hold time too
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CMOS VLSI for Computer Engineering 5 Solutions Reduce clock skew Careful clock distribution network design Plenty of metal wiring resources Analyze clock skew Only budget actual, not worst case skews Local vs. global skew budgets Tolerate clock skew Choose circuit structures insensitive to skew
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CMOS VLSI for Computer Engineering 6 Clock Dist. Networks Ad hoc Grids H-tree Hybrid
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lecture9_PLL_DLL - CMOS VLSI For Computer Engineering...

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