lecture9_sram

lecture9_sram - Lecture 9: SRAM Parts from

Info iconThis preview shows pages 1–11. Sign up to view the full content.

View Full Document Right Arrow Icon
Lecture 9: SRAM Parts from http://www3.hmc.edu/~harris/cmosvlsi/ 4e/index.html
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
CMOS VLSI for Computer Engineering Outline Memory Arrays SRAM Architecture SRAM Cell Decoders Column Circuitry Multiple Ports Serial Access Memories 19: SRAM 2
Background image of page 2
CMOS VLSI for Computer Engineering Memory Arrays 19: SRAM 3 Memory Arrays Random Access Memory Serial Access Memory Content Addressable Memory (CAM) Read/Write Memory (RAM) (Volatile) Read Only Memory (ROM) (Nonvolatile) Static RAM (SRAM) Dynamic RAM (DRAM) Shift Registers Queues First In First Out (FIFO) Last In First Out (LIFO) Serial In Parallel Out (SIPO) Parallel In Serial Out (PISO) Mask ROM Programmable ROM (PROM) Erasable Programmable ROM (EPROM) Electrically Erasable Programmable ROM (EEPROM) Flash ROM
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
CMOS VLSI for Computer Engineering Array Architecture 2 n words of 2 m bits each If n >> m, fold by 2 k into fewer rows of more columns Good regularity – easy to design Very high density if good cells are used 19: SRAM 4
Background image of page 4
CMOS VLSI for Computer Engineering 12T SRAM Cell Basic building block: SRAM Cell Holds one bit of information, like a latch Must be read and written 12-transistor (12T) SRAM cell Use a simple latch connected to bitline 46 x 75 λ unit cell 19: SRAM 5 bit write write_b read read_b
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
CMOS VLSI for Computer Engineering 6T SRAM Cell Cell size accounts for most of array size Reduce cell size at expense of complexity 6T SRAM Cell Used in most commercial chips Data stored in cross-coupled inverters Read: Precharge bit, bit_b Raise wordline Write: Drive data onto bit, bit_b Raise wordline 19: SRAM 6 bit bit_b word
Background image of page 6
CMOS VLSI for Computer Engineering SRAM Read Precharge both bitlines high Then turn on wordline One of the two bitlines will be pulled down by the cell Ex: A = 0, A_b = 1 bit discharges, bit_b stays high But A bumps up slightly Read stability A must not flip N1 >> N2 19: SRAM 7 bit bit_b N1 N2 P1 A P2 N3 N4 A_b word 0.0 0.5 1.0 1.5 0 100 200 300 400 500 600 time (ps) word bit A A_b bit_b
Background image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
CMOS VLSI for Computer Engineering SRAM Write Drive one bitline high, the other low Then turn on wordline Bitlines overpower cell with new value Ex: A = 0, A_b = 1, bit = 1, bit_b = 0 Force A_b low, then A rises high Writability Must overpower feedback inverter N2 >> P1 19: SRAM 8 time (ps) word A A_b bit_b 0.0 0.5 1.0 1.5 0 100 200 300 400 500 600 700 bit bit_b N1 N2 P1 A P2 N3 N4 A_b word
Background image of page 8
CMOS VLSI for Computer Engineering SRAM Sizing High bitlines must not overpower inverters during reads But low bitlines must write new value into cell 19: SRAM 9 bit bit_b med A weak strong med A_b word
Background image of page 9

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
CMOS VLSI for Computer Engineering SRAM Column Example
Background image of page 10
Image of page 11
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 44

lecture9_sram - Lecture 9: SRAM Parts from

This preview shows document pages 1 - 11. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online