ECE_220A_Matrls_215A_Homework-NMOS_Project_2011

ECE_220A_Matrls_215A_Homework-NMOS_Project_2011 - ECE...

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ECE 220A/MAT 215A NMOS Transistor Fabrication of NMOS Transistors DUE: Friday, December 2 nd , 2011 Paper copies of the homework must be handed in class and an electronic version uploaded on Gaucho Space This lab will give you the chance to put together all of the component processing knowledge you have been learning throughout the quarter, and carry out a multi-mask level process to produce an MOS Transistor. The principal processing steps are indicated below, and all of the critical procedures are provided in detailed documents that will be available on the class website. It is up to you and your groups to design a plan and procedure that will calibrate and verify critical steps in the process. For example, - Are you certain that the rate you assume for etching an oxide actually is the actual rate? - Do you really know the thickness of the gate oxide you have formed? - Are your metal interconnects really making contact to the doped-semiconductor, or are they making contact to a thin oxide on top of the semiconductor? You probably know by now that not every process step goes smoothly, and that nominal etch rates, deposition rates, oxidation rates, etc. may not be the actual values that you obtain for your samples. Take that into account in the design of your lab procedures, so that you have the best chance of measuring at least one good transistor. The starting material will be a wafer of p-type <100> silicon with resistivity about 10-30 ohm-cm. Clean your samples. Etch off the native oxide and measure the resistivity of the wafer, using a four point probe. Divide the wafer into the appropriate number of samples that will allow you to characterize the process,
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ECE_220A_Matrls_215A_Homework-NMOS_Project_2011 - ECE...

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