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mdt2_2011solns

# mdt2_2011solns - ECE 260A 20110.101.1020 J Eldon Midterm#12...

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ECE 260A J. Eldon 201 1 0 .1 0 1 . 10 20 Midterm # 1 2 of 2 1. Written in the VERIfyLOGic HDL, a conventional 4-bit binary sequence looks like: 4’h0, 4’h1, 4’h2, … , 4’he, 4’hf. The corresponding Gray code sequence is: 4’h0, 4’h1, 4’h3, 4’h2, 4’h6, 4’h7, 4’h5, 4’h4, 4’hc, 4’hd, 4’hf, 4’he, 4’ha, 4’hb, 4’h9, 4’h8. a. Write a logic expression for generating each bit of Gray code from the corresponding binary count – four expressions in all (easy). Write a logic expression for generating each bit of binary code from the corresponding Gray count – four expressions in all (harder). 2. The truth table for the bit slice of a masking correlator looks like: Mask Ain Bin Out 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 1 a. Write a minimal logic expression for Out = f(Mask, Ain, Bin) b. Sketch a transistor level CMOS logic schematic for this function. 3. Sketch a transistor level schematic for each of the following functions: a. Y = !(ABC+D) ! = “not” b. Y = !(AB+C(A+B)) 4. Given the basic 8-transistor schematic for a 4-input CMOS NOR gate, size the p devices to give an effective pull-up resistance equal to the (N device) pull-down resistance. Assume the N transistors have twice the mobility of the Ps and a normalized size of 2. 5. Consider the pictured RC network: 10k 10k 10k 10k 5p 15p 5p a. Write an algebraic expression for the Elmore delay. b. What is the corresponding time constant?

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Consider an inverter with a size 15 P and a size 5 N. What are the logical efforts for rising and falling transitions? Does this device have high skew, neutral skew, or low skew?
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mdt2_2011solns - ECE 260A 20110.101.1020 J Eldon Midterm#12...

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