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01_overview_p6

01_overview_p6 - Chip Correctness From Design Verification...

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1 © K.T. Tim Cheng 01_overview, v1.0 Chip Correctness – From Design Verification to Lifetime Resiliency 2 © K.T. Tim Cheng 01_overview, v1.0 Overview of IC Testing Types of Testing at IC level IC Production Test Process Burn-in Outline - Overview 3 © K.T. Tim Cheng 01_overview, v1.0 Burn in Board, System and Field Testing Costs of Testing The Testing Problems Verification vs. Testing z Verifies correctness of design. z Performed by simulation, hardware emulation or formal z Verifies correctness of manufactured hardware. z Two-part process: 1. Test generation: software process executed once during Verification Testing 4 © K.T. Tim Cheng 01_overview, v1.0 emulation, or formal methods. z Performed once prior to manufacturing. z Responsible for quality of design. design 2. Test application: electrical tests applied to hardware z Test application performed on every manufactured device. z Responsible for quality of devices. *from M. Bushnell/V. Agrawal Testing Process Is Never Perfect z Based on analyzable fault models, which may not map on real defects. z Incomplete coverage of modeled faults due to high complexity. z Some good chips are rejected The 5 © K.T. Tim Cheng 01_overview, v1.0 Some good chips are rejected. fraction (or percentage) of such chips is called the yield loss. z Some bad chips pass tests. The fraction (or percentage) of bad chips among all passing chips is called the defect level. Testing as Filter Process Good chips Prob(good) = y Prob(pass test) = high Mostly good chips 6 © K.T. Tim Cheng 01_overview, v1.0 Fabricated chips Defective chips Prob(bad) = 1- y Prob(fail test) = high Mostly bad chips Ack: Bushnell and Agrawal, Essential of Electronic Testing, 2000
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