05_comb_tg_p6

05_comb_tg_p6 - Outline – Automatic Test Pattern...

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Unformatted text preview: Outline – Automatic Test Pattern Generation • Test generation systems • Test generation for combinational ckts – – – – D-Algorithm PODEM Boolean Satisfiability approach Test compaction • Test generation for sequential ckts – – – – © K.T. Tim Cheng, 05_comb_tg, v1.0 1 © K.T. Tim Cheng, Time-frame expansion & Extended D-Algorithm Nine-valued test generation Potential detection Issues of sequential ATPG 2 05_comb_tg, v1.0 The ATPG Problem Test Generation Systems • Problem definition: Given a logical fault model, and a circuit, determine a small set of test vectors that detect all faults in the circuit. Compacter • Problem complexity: Under the stuck-at fault model, the problem is NP-complete even for combinational circuits Circuit Description ATPG With fault simulator Test Patterns – However, commercial test generators that efficiently generate tests for >10M-gate ckts are in use today. Fault List Aborted Faults Redundant Faults Undetected Faults Backtrack Distribution Ack: Bushnell and Agrawal, Essential of Electronic Testing, 2000 © K.T. Tim Cheng, 05_comb_tg, v1.0 3 Basics: Path Sensitization Method © K.T. Tim Cheng, A Simple Example D Atomic operations: 1. Activation, fault excitation: Specify inputs so as to A B C generate the appropriate value at fault site for fault excitation (I.e. set S to 1 for S-stuck-at-0 fault) G5 f1 G1 a X s.a.1 G6 f2 E propagate the fault effect from the fault site to the outputs/observation points (1) Fault activation : A = B = C = 1 (2) Have a choice of error propagating: through G5 or G6 3. Line justification: Specify input values so as to produce (a) Propagating through G5 requires G2 = 1 ⇒ A=D=0 ⇒ contradiction the signal values specified in (1) or (2) (b) Propagating through G6 requires G4 = 1 ⇒ C=1, E=0 4. Value implication: unique determination of values at ⇒ Test ABCDE=(111x0) other signals due to value assignments made in (1), (2), or (3) 05_comb_tg, v1.0 G2 G3 2. Error propagation: specify additional signal values to © K.T. Tim Cheng, 4 05_comb_tg, v1.0 5 © K.T. Tim Cheng, 05_comb_tg, v1.0 6 1 Line Justification B H Completeness of ATPG Algorithms G3 A F • E s-a-1 ⇒ E =0 C D E • A test generation algorithm is deemed complete iff it will find a test for a fault if exists or prove that there exists no test, given sufficient time. G4 G2 G1 – Complete algorithms can identify untestable faults • C = D = 1 to propagate through G1. • To propagate G4, need G2 = G3 = 1 Attempt to line justify G2 = G3 = 1 – G3 = 1possible if A = F = 1 or B = H = 1 • Major complete algorithms for comb. ckts – D-algorithm (Roth, 1966) – PODEM (Goel, 1981) • If A = F = 1 ⇒ inconsistency since C = 1 so G2 = 0. – FAN (Fujiwara, 1983) ⇒ Therefore, G3 = 1 ⇒ B = H = 1 – G2 = 1 need A = 0 or F = 0 – Socrates (Schulz, 1988) – Boolean-SAT-based ATPG (Larrabee, 1992) ⇒ Tests are ABCDEH, BCDEFH © K.T. Tim Cheng, 7 05_comb_tg, v1.0 Single Path Sensitization Is NOT Complete C G1 G3 x d s.a.0 G6 G4 d f G2 G5 E C • d s-a-0 : ⇒ A = B = 1 • Propagate along G3, G6 requires C =1, G2 = G4 = G5 = 1. – In order for G4 = 1 either E = 0 or G1 = 0 ⇒ inconsistency ⇒ E = 0, B = 1 ⇒ G5 = 0 ⇒ inconsistency • Propagate along G4, G6 ⇒ E = 1 & G2 = G3 = G5 = 1 – G2 = 1 ⇒ C = 1, ABC = 111 ⇒ G3 = 0 inconsistency ⇒ No test © K.T. Tim Cheng, 05_comb_tg, v1.0 A B G2 A B 1 1 G1 1 9 E 1 0/1 G4 0 G5 1 © K.T. Tim Cheng, G6 G3 d s-a-0 1 G6 G4 0 G5 0/1 1 10 05_comb_tg, v1.0 0/1 D 1 D D D 05_comb_tg, v1.0 0/1 1/0 1/0 1/0 • D represents a signal which has value 1 in normal (fault-free, good) ckt, and value 0 in faulty ckt. (I.e. D ≡ 1/0); Similarly, D ≡ 0/1 • Two paths G3, G2 and G4, G6 are sensitized, i.e. error is propagated along both paths. © K.T. Tim Cheng, 1 0 • Need to be able to deal with multiple “errors” at the inputs to a gate. 1/0 1/0 1/0 G1 1 The D-Algebra 1 0 G3 d s-a-0 1 E Multiple Path Sensitization C 8 05_comb_tg, v1.0 But Boolean Difference Method Finds Test ABCD=(1111)!! G2 A B © K.T. Tim Cheng, D D D D D D D D 0 D D D 1 D • Behaves like a Boolean variable. 11 © K.T. Tim Cheng, 05_comb_tg, v1.0 12 2 8 H J9 An Example Primitive D-cubes • Specifies the minimal input conditions which must be applies to a logic element E in order to produce an error signal at the output of E G1 s-a-0 : 1 3 4 0 X X 2 0 X X 0 5 6 1 1 1 7 G6 G2 8 X D 0 1 X 1 X 1 1 0 0 0 primitive cubes of G4 1 X 1 1 0 0 0 X 0 0 1 primitive cubes of G5 X 1 0 0 1 0 primitive cubes of G6 X 0 X 13 05_comb_tg, v1.0 © K.T. Tim Cheng, The D-Algorithm 0 0 1 © K.T. Tim Cheng, 13 F 11 6 9 10 11 12 13 1 12 1 1 1 primitive cubes of G3 • The propagation D-cubes of a logic element E specify minimal input conditions which are required to propagate an error signal on an input (or inputs) to the output of that element. s.a.0 7 1 X X primitive D-cube 1 G5 10 G3 5 C3 E4 primitive cubes of G2 Propagation D-cubes G4 G1 A1 B 2 1 1 14 05_comb_tg, v1.0 D-Algorithm Example 1) Select a primitive D-cube of the fault 2) Implication and checking for inconsistency. If inconsistency occurs, go to (1). 3) D-drive: selects an element in D-frontier & attempts to propagate D or D in its inputs to its output. D-frontier consists of set of all elements whose output values are unspecified but inputs have some signals with D or D. D-drive is done by intersecting the test cube with a propagation D-cube of the selected element. Backtrack, i.e. select another propagation D-cube, if intersection is null. 4) Implication of D-drive: perform implication for the new test cube. 5) Repeat 3) & 4) until faulty signal propagated to an output. 6) Line justification: Consistency check on input conditions required. © K.T. Tim Cheng, A1 B 2 10 5 G2 5 s.a.0 G2 C3 E4 © K.T. Tim Cheng, G3 G5 G3 G5 G6 6 12 7 13 F 11 16 05_comb_tg, v1.0 G6 6 • Now D-frontier is G5 & G6 12 • Select G5 and a propagation D-cube of G5 7 13 F 11 1 2 3 4 5 6 7 8 9 10 11 12 13 perform implication 1 1 1 1 D 0 D propagation D-cube of G5 1 D D 1 D Test cube after D-drive 1 1 1 1 D 0 D 1 2 3 4 5 6 7 8 9 10 11 12 13 initial test cube ti 1 1 D propagation D-cube of G3 D0D test cube after D-drive 1 1 through G3 = tc' D0D 1 Line justification 1 1 1 1 D 0 D 1 or 1111D0D 11 perform implication 1 1 1 1 D 0 D • Check implication: D-cube of G1 does not imply any other signal. • D-frontier : G3 • Get propagation D-cube for G3 © K.T. Tim Cheng, 10 G1 G4 G1 s.a.0 C3 E4 G4 A1 B 2 15 05_comb_tg, v1.0 8 H J9 8 H J9 05_comb_tg, v1.0 8 H J9 A1 B 2 17 D D G4 10 G1 C3 E4 © K.T. Tim Cheng, 5 s.a.0 G2 G3 G5 G6 6 12 7 13 F 11 05_comb_tg, v1.0 18 3 Line Justification Flowchart for D-algorithm start Begin Initialize test cube (tc) Is there any line in tc which are not justified Select a primitive D-cube of that as C Is there a D or D on any PO ? no yes Line Justification impossible 19 primitive D-cube (1) implication (2) 1 implication (4) 1 111 X implication (5) G4 G1 2 3 6 s-a-1 4 G3 7 G5 G7 111 0D 9 12 10 11 inconsistent & backtrack to (6) 1 1 1 D D 0 1 1D 1D11D 1D11D H A B 00D01D11D 00D01D11D 0 1 0D 1 D 20 05_comb_tg, v1.0 • Since the assignment of values is allowed to internal lines, more than one choice is available at such internal line/gate and backtracking could occur at each gate • Could result in inefficiency for large ckts and some special classes of ckts. • Example: An ECAT (error-correction-&-translation) ckt D 0 1 0D01D11D D 1 1 Implication Line justification (7) 1 1 1 Implication Line justification (8) 1 1 1 implication (8) 1 1 1 1 G8 G6 0D Select D-frontier G8 (6) 5 G2 0 0D 0 111 8 Select D-frontier G5 (3) 1 111 D D D © K.T. Tim Cheng, Potential Problems with D-Algorithm 1 2 3 4 5 6 7 8 9 10 11 12 11 D 11 inconsistent consistent Backtrack to the last Line point a choice exists justification none exists impossible 05_comb_tg, v1.0 A D-Algorithm Example 1 Intersect C with previous test cube tc done Test has been generated Select a gate from D-frontier and a propagation D-cube of the selected gate as C none exists © K.T. Tim Cheng, Select an unjustified line and a primitive cube C to justify the line consistent Backtrack to the last point a choice exists Test has been generated yes D-intersect C with previous test cube tc and perform implication inconsistent no s.a.0 C E J D Select D-frontier G6 (9) 11110D 1DD 1 1 0 implication (10) 0 N K F G 1D P R Q L M 11110D01DD1D Test is found : 1 1 1 1 © K.T. Tim Cheng, 21 05_comb_tg, v1.0 The PODEM Algorithm (Goel 1981) © K.T. Tim Cheng, PODEM Decision Tree for the Example • Only allows assignment of values to primary inputs • The values assigned to primary inputs are then propagated toward internal lines by the implication. Start A=0 © K.T. Tim Cheng, 05_comb_tg, v1.0 A=1 A B C E B=1 C=1 A B P E=0 J K F G H s.a.0 C E H s.a.0 P B=0 • Example: First, a binary value is assigned to an unassigned PI to provide a fault effect at fault site: A = 1 Determine the implications of assigned PIs (only forward implication): A= 1 cause no implication Next, assign B = 1 A = B = 1 ⇒ imply H = D 22 05_comb_tg, v1.0 E=1 N R Q L J K F G N F=0 R Q F=1 M G=0 L G=1 Test has been Successfully generated M 23 © K.T. Tim Cheng, 05_comb_tg, v1.0 24 4 Flowchart of PODEM PODEM Start • Essentially a process of finding a PI & a binary Assign a binary value to an unassigned PI value for initial assignment. Determine implication of all PIs • Continue assigning PI values, checking to see if the error is being propagated to outputs (after each PI assignment, perform forward implication) yes Test is found • If at any stage, either the fault cannot be excited or the error cannot be propagated further, backtrack to the most recent PI assignment and No test exists change it. © K.T. Tim Cheng, 25 05_comb_tg, v1.0 Is objective line A fed by a yes no (fed by PI ? gate G) Current OR/NAND & V=1 objective value V AND/NOR & V=0 and type of gate driving Exit Next obj line is objective the input of G line ? which is at x OR/NAND & V=0 AND/NOR & V=1 and is the easiest to control Next obj line is the input of G Is G which is at x a NAND/NOR and is the gate ? hardest to control yes objective is directed toward providing the fault effect on the faulty line. (2) Given the initial objective, a PI & a logic value are chosen that have a good likelihood of meeting the object. – Done using the backtrace procedure. no Next obj value is the same as the current objective value 27 05_comb_tg, v1.0 • Initial objective: (0, G2) • Implication: G2 = D © K.T. Tim Cheng, G4 G1 X1 X2 X3 G5 G2 X4 • D-frontier is { G5, G6 } • Attempt to propagate through G5 – Require X1 = 1 s-a-1 G8 Z1 G6 • • • • • 28 G4 X2 = 1 G7 G1 X1 X2 X3 = 1 Decision tree • Attempt to propagate D through G8 X4 = 1 29 © K.T. Tim Cheng, X3 X1 = 1 test is found 05_comb_tg, v1.0 A 05_comb_tg, v1.0 Initial objective: ( 1, G6 ) Backtrace to set X4 = 0 Implication: G3 = 1, G7 = 0 & G8 = 1 ⇒ failed in propagating error Backtrack to most recent PI assignment ⇒ reassign X4 = 1 Implication: G3 = 0, G6 = D, G8 = D ⇒ Test is generated G3 • Implication: G1 = 0, G4 = 1, G5 = D © K.T. Tim Cheng, Next obj value is the complement of the current objective value A PODEM Example – Cont’d A PODEM Example • Backtrace: X3 = 1 26 05_comb_tg, v1.0 begin effect has not appeared at fault site, the initial • Initial objective: (0, G2) Is there an untried combination of values on assigned PIs? no yes Set untried combination of values on assigned PIs Found PI initial assignment is the current objective value (1) Determine an initial objective. If the fault • Backtrace to PI : X2 = 1 no Test possible with additional maybe no assigned PIs ? Flowchart of Backtrace Steps in PODEM © K.T. Tim Cheng, © K.T. Tim Cheng, Is there a D or D on any P0 ? 05_comb_tg, v1.0 X4 = 0 G5 G2 X4 conflict & backtrack G8 s-a-1 Z1 G6 G3 G7 30 5 Cost of ATPG Accelerating Comb. ATPG (A) How long? (Time complexity) Basic goals: (B) How much RAM? (Space complexity) • Reduce number of backtracks (C) How many vectors generated? (Test application time) • Reduce processing between backtracking • Theoretical result (Ibarra & Sahni, 1975) : – Generating a test for comb. ckt is NP-complete • Worst-case time ∝ constantG Basic tools: • Topological analysis (G = # of gates) • Emperical result (average-time behavior): • Multiple backtrace – Total ATPG time ∝ constant • G2 • Learning – Test length ∝ G © K.T. Tim Cheng, 31 05_comb_tg, v1.0 Socrates: Static Learning bX a1 c X bX X d X f X e c X During ATPG: aX c © K.T. Tim Cheng, X bX X d 0 f X e ⇒ • Step 1: Construct a formula expressing the Boolean Difference of a circuit with respect to the fault a0 c X • Step 2: Apply a Boolean Satisfiability (SAT) solver to the resulting formula 1 f 1 e Learned information (a=1⇒f=1)⇔(f=0⇒a=0) bX Given a fault, it consists of two steps: 1 d ⇒a 1 32 05_comb_tg, v1.0 Boolean Satisfiability Approach Preprocessing the ckt: (1) Assign a logic value to a certain signal of the ckt (2) Perform all implications from that assignment (3) Learn from the results of implications – Using law of contraposition: (A ⇒ B ) ⇔ (!B ⇒ !A) Preprocessing: © K.T. Tim Cheng, X d 0 f X e 33 05_comb_tg, v1.0 © K.T. Tim Cheng, 34 05_comb_tg, v1.0 Step 1: Extracting the formula – Cont’d Step 1 : Extracting the formula (a) Construct the formula of the good circuit output X A • Each node of the ckt is tagged with the logic formula in 3-element conjunctive normal form, or 3CNF B (D+A) * (D+B) * (D+A+B) D (X+D) * (X+E) * (X+D+E) • The formula is true iff the values assigned are consistent with the truth for the logic element X E C (C+E) * (C+E) (b) Construct formula of faulty circuit output X’ for fault D A B C (C + A) * (C + B) * (C +A + B) A B stuck-at-0 (no need to repeat the part identical to (a)) C (C + A) * (C + B) * (C + A + B) A C A B (D+A) * (D+B) * (D+A+B) 1 D (C + A) * (C + A ) D' (X'+D') * (X'+E) * (X'+D'+E) X' E C © K.T. Tim Cheng, 05_comb_tg, v1.0 35 © K.T. Tim Cheng, (C+E) * (C+E) 05_comb_tg, v1.0 36 6 Step 1: Extracting the formula – Cont’d Step 2: Satisfying the Formula - Boolean Satisfiability (c) Construct the formula of the Boolean Difference: XOR of (a) & (b) and the output of XOR should be 1 X X’ From (a): • Given a suitable representation for a Boolean function f(X): BD=(X+X’) (X+X’)=V1 V2=1 – Find an assignment X* such that f(X*) = 1 – Or prove that such an assignment does not exist (i.e. f(X) = 0 for all possible assignments) (X+D) (X+E) (X+D+E) (D+A) (D+B) (D+A+B) (C+E) (C+E) From (b): • In the “classical” SAT problem, f(X) is represented in product-ofsums (POS) or conjunctive normal form (CNF) (X’+D’) (X’+E) (X’+D’+E) D’ From (c): • Many decision (yes/no) problems can be formulated either directly or indirectly in terms of Boolean Satisfiability (V1+X) (V1+X’) (V1+X+X’) (V2+X) (V2+X’) (V2+X+X’) (BD+V1) (BD+V2) (note: BD=X⊕X’=(X+X’) (X+X’)=V1 V2) (BD+V1+V2) BD © K.T. Tim Cheng, 37 05_comb_tg, v1.0 Conjunctive Normal Form (CNF) © K.T. Tim Cheng, 38 05_comb_tg, v1.0 Literal & Clause Classification ϕ = ( a + c ) ( b + c ) (¬a + ¬b + ¬c ) violated satisfied unresolved satisfied ϕ = (a + ¬b)(¬a + b + ¬c )(a + c + d )(¬a + ¬b + ¬c ) Positive Literal Clause Negative Literal a assigned 0c and d unassigned b assigned 1 * Source: João Marques-Silva and Karem A. Sakallah, “Boolean Satisfiability in EDA”, CAV2000 tutorial. © K.T. Tim Cheng, * Source: João Marques-Silva and Karem A. Sakallah, “Boolean Satisfiability in EDA”, CAV2000 tutorial. 39 05_comb_tg, v1.0 Basic Backtracking Search 1 2 4 5 (a + c + d) (¬a + c + d) 6 (¬a + c + ¬d) 7 (¬b + ¬c + ¬d) 8 • An unresolved clause is unit if it has exactly one unassigned literal a (¬a + b + ¬c) 40 05_comb_tg, v1.0 Unit Clause Rule - Implications (a + b + c ) 3 © K.T. Tim Cheng, (¬b + ¬c + d) (a + b + ¬ c ) b c d b c d c d d ϕ = (a + c)(b + c)(¬a + ¬b + ¬c) • A unit clause has exactly one option for being satisfied a b → ¬c i.e. c must be set to 0. d * Source: João Marques-Silva and Karem A. Sakallah, “Boolean Satisfiability in EDA”, CAV2000 tutorial. * Source: João Marques-Silva and Karem A. Sakallah, “Boolean Satisfiability in EDA”, CAV2000 tutorial. © K.T. Tim Cheng, 05_comb_tg, v1.0 41 © K.T. Tim Cheng, 05_comb_tg, v1.0 42 7 Basic Search with Implications 2 3 (¬a + b + ¬c) 4 5 (a + c + d) (¬a + c + d) 6 (¬a + c + ¬d) 7 (¬b + ¬c + ¬d) 8 (¬b + ¬c + d) • C-SAT: Combinational Circuit-based SAT Solver a (a + b + c ) (a + b + ¬ c ) 1 Public Released SAT Solvers by UCSB b – F. Lu, Li-C. Wang, K.-T Cheng, and R. Huang, “A Circuit SAT solver with Signal Correlation guided learning,” DATE, March 2003. b c – F. Lu, L.-C. Wang, K.-T. Cheng, J. Moondanos and Z. Hanna, "A Signal Correlation Guided ATPG Solver and Its Applications for Solving Difficult Industrial Cases," DAC, Jun. 2003. c • Satori & Satori2: Sequential Circuit-based SAT Solver a b 4 3 5 7 b c 4 3 5 7 d c 6 5 8 5 6 8 8 6 6 d – M. K. Iyer, G. Parthasarathy, and K.-T Cheng, “SATORI—A Fast Sequential SAT solver for Circuits,” ICCAD, Nov. 2003. 6 6 – F. Lu, G Parthasarathy, M. K. Iyer, L.-C. Wang, K.-T. Cheng, "A Efficient Sequential SAT Solver With Improved Search Stategies", UCSB Technical Report, Dec. 2003 * Source: João Marques-Silva and Karem A. Sakallah, “Boolean Satisfiability in EDA”, CAV2000 tutorial. © K.T. Tim Cheng, 05_comb_tg, v1.0 43 © K.T. Tim Cheng, 05_comb_tg, v1.0 44 Test Compaction for Comb. Tests • Fault simulate test patterns in reverse order of generation – ATPG patterns go first – Randomly-generated patterns go last (because they may have less coverage) – When coverage reaches 100%, drop remaining patterns (which are the useless random ones) – Could significantly shortens test sequence – reducing test application time © K.T. Tim Cheng, 05_comb_tg, v1.0 45 8 ...
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This note was uploaded on 01/16/2012 for the course ECE 255a taught by Professor Timcheng during the Fall '11 term at UCSB.

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