07_seq_tg_p6

07_seq_tg_p6 - Outline Test Pattern Generation for...

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© K.T. Tim Cheng 1 © K.T. Tim Cheng 07_seq_tg, v1.0 2 Outline –Test Pattern Generation for Sequential Ckts • Time-frame expansion & Extended D-Algorithm • Nine-valued test generation • Potential detection • Issues of sequential ATPG • Test sequence compaction © K.T. Tim Cheng 07_seq_tg, v1.0 3 Sequential Test Generation: Taxonomy sequential synchronous (or almost synchronous) asynchronous gate level RTL/ gate level state transition level known initial state unknown initial state simulation based approach time-frame expansion based approach simulation based approach © K.T. Tim Cheng 07_seq_tg, v1.0 4 Test Generation Using Time-Frame-Expansion Model Extended D Algorithm ± Select a target fault f ± Create a copy of a combinational logic, set it to time-frame 0 ± Generate a test for f for time-frame 0 using a combinational algorithm ± If the fault effect is propagated to the flip-flops, continue fault propagation in the next time-frame ± If there are values required in the flip-flops, continue the justification in the previous time-frame © K.T. Tim Cheng 07_seq_tg, v1.0 5 An Example FF FF 1 2 Y Y 1 2 IN OUT y y 1 2 X s.a.1 © K.T. Tim Cheng 07_seq_tg, v1.0 6 Example: Step 1 IN OUT s.a.1 Time Frame 0 0 0 D D 0 1 X
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© K.T. Tim Cheng 07_seq_tg, v1.0 7 Example: Step 2 IN OUT X s.a.1 Time Frame 1 1 1 D 1 IN OUT s.a.1 Time Frame 0 0 0 0 1 D D D X © K.T. Tim Cheng 07_seq_tg, v1.0 8 Example: Step 3 IN OUT X s.a.1 Time Frame 1 1 1 D 1 Time Frame 0 IN OUT s.a.1 0 0 0 1 D D D IN OUT X -1 -1 0 0 Time Frame -1 X © K.T. Tim Cheng 07_seq_tg, v1.0 9 An Example that Extended D-Algorithm Fails a b s.a.1 FF 0 0 FF o ab f a u l t - free faulty fault- V 1 00 0 U 1 1 V 2 01 1 U 0 1 © K.T. Tim Cheng 07_seq_tg, v1.0 10 Test Generation using Extended D-Algorithm (Five-Valued Logic) a b s.a.1 D D 1 D D 10 . . . . a b 1 0 0 0 s.a.1 Conflict 1 0 0 No Test © K.T. Tim Cheng 07_seq_tg, v1.0 11 Nine-Valued D-Algorithm (Muth, IEEE TC, June 1976) • Extended D-Algorithm is not complete • If nine-value, instead of five-value, is used, it will be a complete algorithm – Ordered pairs of states of the fault-free and faulty circuits (0/0, 0/1, 0/X, 1/0, 1/1, 1/X, X/0, X/1, X/X) – A superset of the five values (0=0/0, 1=1/1, X=X/X, D=1/0, D=0/1) used in the D-Algorithm – Take into account the possible repeated effects of the fault in the iterative array model © K.T. Tim Cheng 07_seq_tg, v1.0 12 Nine-Value Test Generation a b s.a.1 1/0 . . . . a b 1/X 0/X s.a.1 No Conflict 0/0 0/X 1/X 1/X 0/X 0/1 1/X 0/1 0/1 0/1 T a b V 1 0 V 2 1
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© K.T. Tim Cheng 07_seq_tg, v1.0 13 General Issues of Sequential ATPG ± May not be able to handle highly sequential ckts ± Consider the SA-0 fault at the most significant bit of a 20- bit counter. ...
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This note was uploaded on 01/16/2012 for the course ECE 255a taught by Professor Timcheng during the Fall '11 term at UCSB.

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07_seq_tg_p6 - Outline Test Pattern Generation for...

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