12_syn_test_p6

12_syn_test_p6 - Logic Synthesis for Testability Synthesis...

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1 K.-T. Cheng 2 K.-T. Cheng 12_syn_test, v1.0 Logic Synthesis for Testability ± Synthesis for full testability – Producing irredundant circuits – Producing robust testable circuits for path delay fault ± Synthesis for easy testability – Improving deterministic or random testability ± Testability and test set preserving logic transformations ± Maximizing sharing of system and test logic 3 K.-T. Cheng 12_syn_test, v1.0 Synthesis for Irredundant Circuits ± Best solution: redundancy removal – Reduce circuit size – Improve testability – Reduce propagation delay, in general – Reduce power dissipation – Test set is pretty much preserved – Significantly faster than constrained logic synthesis ± Practical for both combinational and sequential circuits 4 K.-T. Cheng 12_syn_test, v1.0 Redundancy Removal - An Example B C A Conflict! 1 1 1 s.a.0 0 0 0 A B C 1 Z Z Z is glitch-free Z may have glitches • Warning: Redundancy may be required for glitch-free designs!! • If having glitches is not a concern (e.g. synchronous designs), redundancy can be removed. 5 K.-T. Cheng 12_syn_test, v1.0 Circuit Simplification Rules Case Operation AND (NAND) input is constant 1 Remove input AND (NAND) input is constant 0 Remove gate and its inputs Propagate constant 0 (1) to each of gate’s fanout Gate has no fanout Remove gate and its inputs Flip-flop input is constant 0 (1) Remove flip-flop and its inputs Propagate constant 0 (1) to each of flip-flop’s fanout If a s-a-1(0) fault is identified as redundant, set the faulty net to logic 1(0), then simplify the network by recursively applying the following rules.
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This note was uploaded on 01/16/2012 for the course ECE 255a taught by Professor Timcheng during the Fall '11 term at UCSB.

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12_syn_test_p6 - Logic Synthesis for Testability Synthesis...

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