This preview shows pages 1–2. Sign up to view the full content.
This preview has intentionally blurred sections. Sign up to view the full version.View Full Document
Unformatted text preview: ECE—2030
Sections E/F Homework Assignment #8
Due: Dec.8 (Thursday) Chapter 7, problems #2,7,l6,23
Chapter 9 problem #11 Be sure that you are using the 4th edition. 7—2. *Perform the bitwise logic AND, OR, and XOR of the two 8—bit operands
10011001and 11000011. @»7—7. A switch-tail counter (also called twisted ring counter, Johnson counter) uses the complement of the serial output of a right shift register as its serial
input. (a) Starting from an initial state of 000, list the sequence of states after each
shift until the register returns to 000. (b) Beginning in state 00.0 , how many states are there in the count
sequence of an n-bit switch-tail counter? (c) Design a decoder to be driven by the counter that produces a one-hot
‘ ' code output for each of the states. Make use of the don’t-care states in your design. 7—16. Draw the logic diagram of a 4-bit register with mode selection inputs S1 and S0. The register is to be operated according to the function table at the top ,of
page 405. S1 80 Register Operation
0 0 No change 0 I 1 Complement output
1 0 Load parallel data 1 1 Clear register to 0 7—23. Logic to implement transfers among three registers, R0, R1, and R2, is to be implemented. Use the control variable assumptions given in Problem 7—18.
The register transfers are as follows: CA: R1<—R0
CB: R0<—R1, R2<——R0
CC: R1<—R2, R0<—R2 Using registers and dedicated multiplexers, draw a detailed logic diagram of
the hardware that implements a single bit of these register transfers. Draw a logic diagram of simple logic that converts the control variables CA, CB, and CC as inputs to outputs that are the SELECT inputs for the
multiplexers and LOAD signals for the registers. 7—18. The outputs of registers R0, R1, R2, and R3 are connected through 4-to-1 9-11. multiplexers to the inputs of a ﬁfth register, R4. Each register is 8 bits long.
The required transfers, as dictated by four control variables, are C0: R4<——RO
C3: R4é—R3' The control variables are mutually exclusive (i.e., only one variable can be
equal to 1 at any time) while the other three are equal to 0. Also, no
transfer into R4 is to occur for all control variables equal to 0. (3) Using
registers and a multiplexer, draw a detailed logic diagram of the hardware
that implements a single bit of these register transfers. (b) Draw a logic
diagram of the simple logic that maps the control variables as inputs to three outputs: the two select variables for the multiplexer and the load
signal for the register R4. Given the sequence of 16-bit control words below for the datapath in
Figure 9-11 and the initial ASCII character codes in 8-bit registers, SImulate
the datapath to determine the alphanumeric characters in the registers
after the execution of the sequence. The result is a scrambled word: what IS
it? 011 011 001 0 0010 0 1 R0 00000000
100 100 001 0 1001 0 1 R1 00100000
101 101 001 0 1010 O 1 R2 01000100
001 001 000 0 1011 0 1 R3 01000111
001 001 000 0 0001 0 1 R4 01010100
110 110 001 0 0101 0 1 R5 01001100
111 111 001 O 0101 0 1 R6 01000001
001 111 000 0 0000 O 1 R7 01001001 ...
View Full Document
This note was uploaded on 01/16/2012 for the course ECE 2030 taught by Professor Wolf during the Fall '07 term at Georgia Institute of Technology.
- Fall '07