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HW9_Practice_Problems_Solutions

# HW9_Practice_Problems_Solutions - ECE 2030 E/F Practice...

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ECE 2030 E/F Practice Problems - Solutions (1) Textbook #5-14 – The State Diagram for a sequential circuit is given in Fig.5-40 (pg.284). (a) Find the State Table . (b) Make 2-bit state assignments, and write the “encoded” state table . (c) Find the optimized circuit using D flip-flops, NANDs and Inverters. Solution: (a) From the given state diagram, we can construct a state “table” by first listing all the possible combinations of present states and input combinations, then for each of these combinations use the diagram to find the next states and output value(s). P.S. Inputs(X1,X2) N.S. Output(Z) P.S. Inputs(X1,X2) N.S. Output(Z) A 0 0 A 0 C 0 0 A 1 A 0 1 B 0 C 0 1 A 0 A 1 0 B 1 C 1 0 C 1 A 1 1 A 0 C 1 1 C 0 B 0 0 A 0 D 0 0 C 1 B 0 1 A 0 D 0 1 B 1 B 1 0 D 1 D 1 0 B 0 B 1 1 D 1 D 1 1 C 1 (b) We use the most obvious assignment of 2-bit codes (not unique), as follows: A(Q1,Q2)=(0,0) B(Q1,Q2)=(0,1) C(Q1,Q2)=(1,0) D(Q1,Q2)=(1,1) Replace the symbols in the table of part (a) with these values to get : P.S. Inputs(X1,X2) N.S. Output(Z) P.S. Inputs(X1,X2) N.S. Output(Z) 00 0 0 00 0 10 0 0 00 1 00 0 1 01 0 10 0 1 00 0 00 1 0 01 1 10 1 0 10 1 00 1 1 00 0 10 1 1 10 0 01 0 0 00 0 11 0 0 10 1 01 0 1 00 0 11 0 1 01 1 01 1 0 11 1 11 1 0 01 0 01 1 1 11 1 11 1 1 10 1 (c) To optimize the NS and Output logic, we construct three four-variable K-maps using the data in the table from part (b), first listing the minterms for each function: D1 = Q1+(Q1,Q2,X1,X2) = ∑ m(6,7,10,11,12,15) D2 = Q2+(Q1,Q2,X1,X2) = ∑ m(1,2,6,7,13,14) Z = ∑ m(2,6,7,8,10,12,13,15) A B 11 D 00/0, 11/0 10/1, 11/0 01/0, 10/1 00/0,01/0 00/1, 01/0 00/1,11/1 10/1, 11/1 Format = X1X2/Z 01/1, 10/0

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When these functions are minimized using K-maps (shown below), we get: D1 = Q1+ = X1Q1’Q2 + X1Q1Q2’ + X1X2Q2 + X1’X2’Q1Q2 Or : = X1Q1’Q2 + X1Q1Q2’ + X1X2Q1 + X1’X2’Q1Q2 D2 = Q2+ = X1’X2Q1’Q2’ + X1’X2Q1Q2 + X1X2’Q1’ + X1X2’Q2 + X1Q1’Q2 Z = X1X2’Q1’ + X1X2Q2 + X1’Q1Q2 + X2’Q1Q2’ Or : = X1X2’Q2’ + X1Q1’Q2 + X2Q1Q2 + X1’X2’Q1 Normally these SOP solutions would be implemented using AND gates followed by OR gates. However, if we insert a pair of inversions between the two types of gates, we can change these solutions to all NAND gates as follows: Z = X1X2’Q1’ + X1X2Q2 + X1’Q1Q2 + X2’Q1Q2’ 1 X1 X2’ Q1’ 5 2 X1 X2 Q2 3 X1’ Q1 Q2 4 X2’ Q1 Q2’ Q1 Q1Q2 X1X2 00 00 01 11 10 X1 01 11 10 Q2 X2 m0 m1 m3 m2 m4 m5 m7 m6 1 m12 m13 m15 m14 m8 m9 m11 m10 1 1 1 1 1 1 1 D1 = X1Q1’ Q2 + X1Q1Q2’ + X1X2Q1 + X1’X2’Q1Q2 1 X1 Q1’ Q2 5 D1 2 X1 Q1 Q2’ 3 X1 X2 Q1 (or Q2) 4 X1’ X2’ Q1 Q2 Q1 Q1Q2 X1X2 00 00 01 11 10 X1 01 11 10 Q2 X2 m0 m1 m3 m2 m4 m5 m7 m6 1 m12 m13 m15 m14 m8 m9 m11 m10 1 1 1 1 1
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HW9_Practice_Problems_Solutions - ECE 2030 E/F Practice...

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