sp_2005_6_152J_ST04_MOSCap - Microelectronics Processing...

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Microelectronics Processing Technology 6.152J / 3.155J Spring 2004 MOSCap01.doc MOS Capacitor Page 1 of 9 Metal Oxide Semiconductor (MOS) Capacitor The MOS capacitor structure is shown in Figure 1. The “metal” plate is a heavily doped n + - poly-silicon layer which behaves as a metal. The insulating layer is silicon dioxide and the other plate of the capacitor is the semiconductor layer which in our case is n-type silicon whose resistivity is 1-10 -cm corresponding to a doping of 10 15 cm -3 . The capacitance of the MOS structure depends on the voltage (bias) on the gate. For the purposes of this discussion, we shall refer to the contact to the semiconductor as the body (B) while the poly-silicon is called the gate (G). Typically a voltage is applied to the gate while the body is grounded and the applied voltage is V G but more accurately V GB . The two (V G & V GB ) will be used interchangeably in this document. n-Si n + -Poly-Si B ody G ate Oxide Figure 1: The MOS Capacitor structure. The substrate (body) is grounded and a voltage V GB is applied to the poly-silicon gate. The capacitance depends on the voltage that is applied to the gate (with respect to the body). The dependence is shown in Figure 2 and there are roughly three regimes of operation separated by two voltages. The regimes are described by what is happening to the semiconductor surface. These are (1) Accumulation in which mobile carriers of the same type as the body accumulates at the surface [electrons] (2) Depletion in which the surface is devoid of any mobile carriers leaving only a space charge or depletion layer, and (3) Inversion in which mobile carriers of the opposite type to the body [holes] aggregate at the surface to “invert” the conductivity type. The two voltages that demarcate the three regimes are (a) Flatband Voltage (V FB ) which separates the accumulation regime from the depletion regime and (b) the Threshold Voltage (V T ) which demarcates the depletion regime from the inversion regime. Let us now look at our particular device MOS capacitor with an n-type body / substrate.
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V GB V T C MOS (V T )=C min V FB Inversion Depletion Accumulation C QS C HF C max C min C max = A C ox C MOS Figure 2: Capacitance vs. Gate Voltage (CV) diagram of a MOS Capacitor. The flatband voltage (V FB ) separates the Accumulation region from the Depletion regime. The threshold voltage (V T ) separates the depletion regime from the inversion regime. C HF is high frequency capacitance while C QS is quasi-static or low frequency capacitance. Surface Accumulation (V GB > V FB ) An applied positive gate voltage larger than the flatband voltage (which will be defined shortly) (V GB > V FB ) induces positive charge on the “metal” gate and negative charge in the semiconductor. The only negative charges available are electrons and they accumulate at the surface. The electron concentration at the surface is above the bulk value, thus leading to a condition that is called surface accumulation . The charge distribution and equivalent circuit is shown in Figure 3. The flatband voltage (V FB
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This note was uploaded on 01/17/2012 for the course EE EE 110 taught by Professor Gupta during the Spring '09 term at UCLA.

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sp_2005_6_152J_ST04_MOSCap - Microelectronics Processing...

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