mt2sol - C -302-701 Solutions to Midterm # 2 Q1. See pdf...

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Unformatted text preview: C -302-701 Solutions to Midterm # 2 Q1. See pdf file for state transition diagram entity SEQDET is port(X,CLK:in bit; Z:out bit); end SEQDET; architecture behav of SEQDET is type next_state is (S0,S1,S2,S3); signal n_s:next_state; begin process(CLK) begin if CLK='1' and CLK'event then case n_s is when S0 => Z <='0'; if (X='0') then n_s <= S1; end if; when S1 => Z <= `0'; if (X='1') then n_s <= S2; end if; when S2 => Z <='0'; if (X='0') then n_s <= S3; elsif (X='1') then n_s <= S0; end if; when S3 => Z <='1'; if (X='0') then n_s <= S1; elsif (X='1') then n_s <= S2; end if; end case; end if; end process; end behav; Q2. (i) process variable i,sum:integer; begin sum:=0; for i in 0 to n loop sum:=sum+2*i; end loop; wait for 100 ns; end process; (ii) process variable i,sum:integer; begin sum:=0; for i in 1 to 2*n loop if (i mod 2)=1 then next; else sum:=sum+i; end if; end loop; wait for 100 ns; end process; Q3. Truth Table for T flipflop T 0 0 1 1 Qi 0 1 0 1 Qi+1 0 1 1 0 Qi+1 = T xor Qi entity TFF is port(T,CLK:in bit;Q, QBAR:buffer bit); end TFF; architecture behav of TFF is begin process(CLK) variable temp:bit; begin temp:=T xor Q; if CLk='1' then Q <=temp; QBAR<=not temp; end if; end process; end behav; See pdf file for circuit diagram of 4 bit counter entity COUNTER is generic(n:natural:=4); port(count:in bit; Z:buffer bit_vector(n-1 down to 0)); end COUNTER; ...
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mt2sol - C -302-701 Solutions to Midterm # 2 Q1. See pdf...

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