hw5+6 - Q5. Study the process given below and answer the...

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C-302-701 Homework Assignment for Weeks 5 and 6 Q1. Model the JK flip-flop with PRESET and CLEAR as a state machine including an undefined state (as discussed in class). Write complete VHDL code for it. Q2 . Model the RS flip-flop as FSM and write VHDL code for it. There should be an ‘Undefined’ state when it is clocked with R = S = ‘1’. It should be possible to come out of this state by clocking with either R= ’1’, S=’0’ or R=’0’, S = ‘1’ Q3. Develop the state machine and write VHDL code for a sequence detector to detect “1011” with and without overlapping sequences Q4 Write a process to find the sum of the first n odd integers (i) using ‘for’ loop (ii) using ‘while’ loop (iii) using ‘exit’ statement (iv) using ‘next’ statement to skip the even integers
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Unformatted text preview: Q5. Study the process given below and answer the questions below: process type vec is array(0 to 3) of integer; variable x:vec := (1,-2,4,2); variable y:vec := (1,-5,3,2); variable s:integer:=0; variable i:integer; variable j:integer:=0; begin assert j=0 report “calculation over” severity failure; i:=0; while i<=2 loop i:=i+1; if (x(i) > y(i)) then s = s + x(i)*y(i); else next; end if; end loop; j:=j+1; wait for 10ns; end process; (i) How many times is the loop executed? (ii)How many times is the ‘next’ statement executed? (iii)What is the value of s after the process executes? (iv)If ‘next’ is replaced by ‘exit’ what would be the answer to part (iii)? (v) Why is the ‘wait’ statement required at the end?...
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This note was uploaded on 01/17/2012 for the course ECEC 302 taught by Professor Karkalprabhu during the Spring '06 term at Drexel.

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hw5+6 - Q5. Study the process given below and answer the...

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