Topic 10a - Multicyle Datapath

Topic 10a - Multicyle Datapath - Computer Architecture...

Info iconThis preview shows pages 1–9. Sign up to view the full content.

View Full Document Right Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: Computer Architecture Multicycle Datapath Reading: See Lectures folder for supplementar A Glance at the Schedule Whats coming in Hw4 due Friday M1 due next Wednesday Announcements In-Class group meetings tomorrow No class on Friday (comp time for evening exam) Outline Problems with single-cycle Steps RTL Home computers are being called upon to perform many new functions, including the consumption of homework formerly eaten by the dog. Doug Larson Single-Cycle Design Problems Assuming fixed-period clock every instruction datapath uses one clock cycle implies: CPI = 1 cycle time determined by length of the longest instruction path (load) but several instructions could run in a shorter clock cycle: waste of time consider if we have more complicated instructions like floating point! resources used more than once in the same cycle need to be duplicated waste of hardware and chip area Fixing the problem with single- cycle designs One solution: a variable-period clock with different cycle times for each instruction class infeasible , as implementing a variable-speed clock is technically difficult Another solution: use a smaller cycle time have different instructions take different numbers of cycles by breaking instructions into steps and fitting each step into one cycle feasible: multicyle approach ! Multicycle Approach Break up the instructions into steps each step takes one clock cycle balance the amount of work to be done in each step/cycle so that they are about equal restrict each cycle to use at most once each major functional unit so that such units do not have to be replicated functional units can be shared between different cycles within one instruction Between steps/cycles At the end of one cycle store data to be used in later cycles of the same instruction need to introduce additional internal (programmer-invisible) registers for this purpose Multicycle Approach Note particularities of multicyle vs. single- diagrams single memory for data and instructions single ALU, no extra adders extra registers to hold data between clock cycles PC Instruction memory Read address...
View Full Document

Page1 / 29

Topic 10a - Multicyle Datapath - Computer Architecture...

This preview shows document pages 1 - 9. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online