Topic 10b - Multicycle Control

Topic 10b - Multicycle Control - Computer Architecture...

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Unformatted text preview: Computer Architecture Multicycle Control Reading: See schedule for supplementar y material. A Glance at the Schedule Whats coming in M1 Hw4 Whats going out M2 Outline Control lines Finite state machine Multicycle Datapath with Control I Shift left 2 MemtoReg IorD MemRead MemWrite PC Memory MemData Write data M u x 1 Registers Write register Write data Read data 1 Read data 2 Read register 1 Read register 2 Instruction [15 11] M u x 1 M u x 1 4 ALUOp ALUSrcB RegDst RegWrite Instruction [150] Instruction [5 0] Sign extend 32 16 Instruction [2521] Instruction [2016] Instruction [150] Instruction register 1 M u x 3 2 ALU control M u x 1 ALU result ALU ALUSrcA Zero A B ALUOut IRWrite Address Memory data register with control lines and the ALU control block added not all control lines are shown Multicycle Datapath with Control II Complete multicycle MIPS datapath (with branch and jump capability) and showing the main control block and all control lines Shift left 2 PC M u x 1 Registers Write register Write data Read data 1 Read data 2 Read register 1 Read register 2 Instruction [15 11] M u x 1 M u x 1 4 Instruction [15 0] Sign extend 32 16 Instruction [25 21] Instruction [20 16] Instruction [15 0] Instruction register ALU control ALU result ALU Zero Memory data register A B IorD MemRead MemWrite MemtoReg PCWriteCond PCWrite IRWrite ALUOp ALUSrcB ALUSrcA RegDst PCSource RegWrite Control Outputs Op [5 0] Instruction [31-26] Instruction [5 0] M u x 2 Jump address [31-0] Instruction [25 0] 26 28 Shift left 2 PC [31-28] 1 1 M u x 3 2 M u x 1 ALUOut Memory MemData Write data Address New multiplexor New gates For the jump address Multicycle Control Step (1): Fetch IR = Memory[PC]; PC = PC + 4; 1 1 1 X X 010 1 5 5 RD1 RD2 RN1 RN2 WN WD RegWrite Registers Operation ALU 3 E X T N D 16 32 Zero RD WD MemRead Memory ADDR MemWrite 5 Instruction I 32 ALUSrcB <<2 PC 4 RegDst 5 I R M D R M U X 1 2 3 M U X 1 M U X 1 A B ALU OUT 1 2 M U X <<2 CONCAT 28 32 M U X 1 ALUSrcA jmpaddr I[25:0] rd MUX 1 rt rs immediate PCSource MemtoReg IorD PCWr* IRWrite Multicycle Control Step (2): Instruction Decode & Register Fetch...
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Topic 10b - Multicycle Control - Computer Architecture...

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