# lecture_07 - ECE 190 Lecture 07 February 8 2011 Digital...

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Unformatted text preview: ECE 190 Lecture 07 February 8, 2011 Digital Logic Structures - ll Lecture Topics 0 Storage elements 0 Memory 0 Sequential logic 0 Clock Lecture materials Textbook § 3.4 — 3.7 Homework HWZ due February 17 at 5pm in the ECE 190 drop-off box Machine problem MP1.2 due February 17 at 5pm submitted electronically. Try to submit it by this Wednesday because you may not have time to work on it during the week of the exam. Announcements Exam is next week. We will post on Compass your day/room assignment Remember you can have one sheet of paper with hand-written notes at the exam. 1 V. Kindratenko ECE 190 , Lecture 07 February 8, 2011 Storage elements MUX with the feedback path as a simple storage element Consider the following circuit in which its output is connected to one of its inputs: 0 when 5:0, the output of MUX equals the value of a 0 when s is flipped to 1, the output of MUX is “latched” via the feedback path to the value it had before. Changing input a does not change output c anymore. This simple circuit in principle can be used to store one bit of information. in practice more elaborate circuits are used. R-S latch Recall NAND truth table: output is 0 only when both inputs are 1. R-S latch is constructed out of two NAMD gates as follows: 0 when inputs s=r=1, R-S latch is said to be in "quiescent" state (quiet state), meaning that it holds its previous value c if previous values of outputs a and b were 1, and current values of inputs r and 5 both turned to 1, output values a and b will flip to 0. The latch will be in an unstable state and the output values will flip again. 0 we say that 0 input r is used to "reset" or "clear" the element, or set it to "0” 0 input sis used to “set” the element, or set it to "1” 2 V. Kindratenko ECE 190 Lecture 07 February 8, 2011 o in summary 0 when r=s=1, R-S latch holds current value 0 when 5:0 and r=1, R—S latch sets value to 1 0 when 5:1 and r=0, R-S latch sets value to 0 0 when r=s=0, R-S latch is in an unusable state, which we should not put it in Gated D latch Gated D latch allows to work with the R—S latch storage element in a more "controlled" way, avoiding the situation when both 5 and r inputs are set to 0. It consists of an R-S latch with two additional NAND gates put in front of it: d we II II 0 here input "we" stand for write-enable, input "d" stands for data value, and output q stands for latch output 0 when we=0, s and r inputs to the R-S latch are set to 1, and the value stored in latch persists 0 when we=1 and d=0: 5:1 and r=1, and thus q=0 — R—S latch stores value 0 0 when we=1 and d=1: 5:0 and r=1, and thus q=1 — R-S latch stores value 1 We will use the following symbolic representation for gated D latch: d 61 we 5 or Register A structure that can be used to store a group of bits d3 d2 d1 do we Q3 cl2 Q1 Go 1 l l l l l l 3 V. Kindratenko I L. 9. p. S 31 g M “6f? VOL-8M1 >10 (M44 Whiz-4'0 g6 ﬂaw! ﬁdwoﬂf‘f-e Vo/‘CW ~_ mi W4 w (w! 21 is y) cwcf W! "57" wLa ; r sew MM W W 10.1) ‘ "’ “411” am! " [EM ‘Lﬂ wie‘._ mi R 'VLO , ' 19. pp g gfc'c/ - a: Cam mall‘o [my/c ~> SeWol/élz éyﬁ \X 1 ' v VOW) ' m Sim/e) 98:14—16 :26L (2 ngvL/M » 1’3 52 lfglxta/JJLDVLV pv[ a/l 6161/46ng a4 :1- 8¢\V&(4 ‘mammvi ('0: ' me . \$ COMGZEW’Zéd' SQWJIM arm/“fig g 07: “*> Cam/62% VLsz {mg/(é, m’ruc/i— ’ “> 940mg 31% egnésrmag ’ j '> a- '(‘wjf Mumgyr. W ; .—>am_€ [/0119 (zil'mz‘ gag/Mia FR (171 8 7% J2, 21ml 9 «WW DQL WM. Jag/mug; ea 0 m V62 we > A ' ' A a P1. C9 (’ng6 ’9 at amt/MW; Wag i0 .9an 5 davbbﬂé {\$wa c42ng awﬁA KAI/m X w ~ y, a! :1 441“ R r j a C —— o it w ff ~ 0 r 5w: -é;0~:mg4%:roaml ULroM/I ludoéé W/oae 0M 'gJ—mie Jo (Mom ‘ 1L ’6 Settle éhcwsaﬁ'owg (’4 ﬂz\$ {gazme @ng’é 1‘3 oLéezrmﬂch a? W aurr‘wvlgéhé alt/14 W CP‘IZCI’MZL (543904 l/tzlcce *2/14. Fg M? 4rth1'J/WM-JVOW (9011 314% 7Z0 (ax/«0%» ('9 «Slum/6’64 aﬂéewwca 0va M exvémw/ [a Will/be. > ' ‘ ’ ~7L‘mémdUg/I'la/ be‘éJWS/ 81 WVZuzm/Sm 141(33/5/5 ,HM .LVMg/Iicrﬂm (Emu/1 0M 344716 149 (WWW £55 a Ml dwoJMM/S c2 anM W! qua/mkg @JM/Ieem salable/g (9 Wolf . 3412/er ogLa Jack cgv/[e I4 m. M. I (OS/MW (2chva Jig/WW : comgv'm: #w/zaz - ' ) ‘12 4063/12 dram”; > 31‘7 § u -- u. . \ Ill h I , , A ‘ _\ - __ h 5o S! E ’ > a - \ ‘ i g 3) Mi S mas an; ve ' ('F— 009 5 6mg & 3" ' ...
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lecture_07 - ECE 190 Lecture 07 February 8 2011 Digital...

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