lecture_08 - ECE190 Lecture08 February10,2011...

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Unformatted text preview: ECE190 Lecture08 February10,2011 The von Neumann model Lecture Topics VonNeumannmodel LC ­3asavonNeumannmachine Lecture materials TextbookCh.4 TextbookAppendixC Homework HW2dueFebruary17at5pmintheECE190drop ­offbox Machine problem MP1.2dueFebruary17at5pmsubmittedelectronically. Announcements Examisnextweek.CheckCompassforyourday/roomexamassignment. Rememberyoucanhaveonesheetofpaperwithhand ­writtennotesattheexam.Nobooksor calculators.      1 V.Kindratenko ECE190 Lecture08 February10,2011 Von Neumann model Concept ThevonNeumannmodel/architecturereferstoacomputerorganizationwhichisbasedonthe stored ­programconcept Stored ­programconceptreferstothecomputerarchitectureinwhichdataandprogramare storedinthesamememory o ThevonNeumannarchitecture stored ­programconcept program ­controlledcomputers o Programmedbysettingswitchesandphysicallyconnectingfunctionalunits Stored ­programdigitalcomputeskepttheirprogram(setofinstructions)anddatainread ­write random ­accessmemory Von Neumann model components Memory storesdataandprogram Processingunit performsthedataprocessing Input meanstoenterdataandprogram Output meanstoextractresults Controlunit controlstheorderoftheinstructionexecution  Controlunit Processingunit PC Temporarystorage IR ALU FSM Memory Inputdevice MDR MAR Outputdevice   2 V.Kindratenko ECE190 Lecture08 February10,2011 Memory Inthelastlecturewebuilta22 ­by ­3 ­bitmemory o 3 ­bitaddressability ateachmemorylocationwecanstore3bitsofinformation o 22addressspace therearethatmanyuniquememorylocationsthatcanbeaddressed individually o Thismemorycanbethoughtofasanarray,orsequenceoflocationsthatare sequentiallynumbered 00 01 address whatisstoredatagiven location 111 10 11 010  noteaddressandthevaluestoredinmemoryatthataddress o Inthisexample,memorylocation  Amoderncomputerwith1GBofmemory o 8 ­bit(onebyte)addressability ateachmemorylocationwecanstoreonebyteofdata o 230addressspace ­230uniquelyaddressablememorylocations Ingeneral,wewillthinkofmemoryasadevicecapableofstoringmn ­bitwords o n addressability o m addressspace o tointeractwiththememory,wewillneedn ­bitdataline,log2m ­bitaddressline,and1 ­ bitWEline data address n m log2m ... WE n   3 V.Kindratenko ECE190 Lecture08 February10,2011 Actualinteractionwithmemoryisimplementedusingtwospecial ­purposeregisters,calledMAR (memoryaddressregister)andMDR(memorydataregister) Toreadavalueformmemory o PlacetheaddressofthememorylocationtoreadfromintheMAR MemorycircuitthenwilltransferdatafrommemorytoMDR o ReadvaluefromMDR Towriteavalue o PlacetheaddressofthememorylocationtowritetointheMAR o PlacethevaluetobestoredinthememoryintheMDR o Assert(setto1)WEsignal MemorycircuitthenwilltransferdatafromMDRtomemory Processing unit Carriesoutactualprocessingofinformation Inthesimplesform,itconsistsoftwomainparts o AnALUthatimplementsafewbasicoperations,suchasADD,AND,etc. Asanexample,LC ­ AND,andNOToperationsonly o Atemporarystorage,typicallyasetoffewregistersforstoringfewwordsofdata Asanexample,LC ­3computerhas8registers o ThesizeofdataitemsprocessedbytheALUisreferredtoasthewordlength,andeach dataitemisreferredtoasaword Asanexample,LC ­3computerhaswordlengthof16bits(ortwobytes) Inamodern64 ­bitmicroprocessor,wordlengthis64bits(or8bytes) Input and Output Inorderforcomputertoprocesstheinformation,theinformationitselfneedstobeentered intothememory Inorderforustoknowtheresultsofprocessingtheinformation,theresultsneedtobeoutput insuchawaythatwecanseethem Toaccomplishthis,computershavesomeformofinputandoutputdevices,genericallyreferred toasperipherals Asanexample,LC ­43computerhaskeyboardasaninputdeviceandmonitorasanoutput device Inthesimplestform,inputandoutputdevicesworkwithmemorydirectly,thatis,aninput deviceplacesavalueintosomememorylocationandanoutputdevicereadsanddisplaysa valuefromsomememorylocation o SuchI/Oisreferredtoasmemory ­mappedI/O Control unit Directstheworkofallotherunits Keepstrackofwhichinstructionisbeingexecuted,andwhichinstructionwillbeprocessednext; forthisitusestwospecial ­purposeregisters  4 V.Kindratenko ECE190 Lecture08 o o o February10,2011 Instructionregister(IR)containscurrentinstructionbeingexecuted Programcounter(PC)registerkeepsapointer(address)tothenextinstructiontobe executed Ingeneral,controlunitcanbethoughtofasalargeFSMandthecontrolunitcycles betweendifferentstatesasitdirectstherestofthecomputertoexecuteagiven instruction LC ­3 as a von Neumann machine Inthiscoursewewillstudyacomputer,calledLittleMachine3,orLC ­3whichisan implementationofthebasicvonNeumannarchitecture:   5 V.Kindratenko ECE190 Lecture08 February10,2011 Stored program concept Programisstoredinsomepartofcomputermemoryasasequenceofinstructions Instructionsarerepresentedandstoredinmemoryasbinarywords Memory Partofmemoryused tostoreinstructions Partofmemoryused tostoredata  Controlunitreadsaninstructionformthememory o InstructionaddressofthenextinstructiontobeexecutedisstoredinPC The Instruction Themostbasicunitofcomputerprocessing Inthesimplestform,consistsoftwoparts o Opcode(operationcode) aportionofamachinelanguageinstructionthatspecifiesthe operationtobeperformed o Operands apartofamachinelanguageinstructionthatspecifiesthedatatobe operatedon LC ­3instructionformatexample o 16 ­bits(onemachineword) o Theleft ­most4bitscontaintheopcode o Therestofthebitsareusedtoencodewheretheoperandsare [15:12] opcode  [11:0] operands 6  V.Kindratenko ECE190 Lecture08 February10,2011 o Example:0001110010000110 0001isanopcode 110010000110 thesebitscontaininformationabouttheoperands Generally,thereare3typesofinstructions: o Operate performsomeoperation,e.g.,ADD o Datamovement,e.g.,loadvalueformmemorytoaregister o Control changethevalueofPC LC ­3 instruction examples ADDinstruction o Requires3operands: Twosourceoperands Onedestinationoperand o Action:R6 R2+R6(valuesstoredinregisters2and6areaddedtogetherandtheresult isplacedintoregister6) 15 ADD 14 13 12 11 10 9 8 7 6 5 0 0 0 1 1 1 0 0 1 0 0 opcode 4 0 3 2 0 1 0 1 1 0 sourceregister1 (R2) destinationregister (R6) sourceregister0 (R6)  LDRinstruction o load,   o Action:R2 MEM[R3+6](addvalue6(offset)tothevaluestoredinregister3(base)and loadvaluefromthecomputermemorystoredattheaddressbase+offsettothe destinationregister2) 15 L DR 14 13 12 11 10 9 8 7 6 5 0 1 1 0 0 1 0 0 1 1 0 opcode 4 0 2 1 0 1 0 baseregister (R3) destinationregister (R2) 3 1 0 offsetvalue(6)  JMPinstruction o Action:PC R3(loadPCwithavaluestoredinregister3) 15 JMP 14 13 12 11 10 9 8 7 6 5 1 1 0 0 0 0 0 0 1 1 0 Registerwithnext instructionaddress (R3) opcode  7 4 0 3 0 2 1 0 0 0 0  V.Kindratenko ECE190 Lecture08 February10,2011 Von Neumann instruction cycle Instructionsareprocessedbythecontrolunitinasystematic,step ­by ­stepmanner Thesequenceofstepsinwhichinstructionsareloadedfrommemoryandexecutediscalled instructioncycle Eachstepinthesequenceisreferredtoasaphase Fundamentally,thereare6phases o FETCH(instruction) o DECODE o EVALUATEADDRESS o FETCHOPERANDS o EXECUTE o STORERESULTS FETCHINSTRUCTIONphase o ObtainthenextinstructionfrommemoryandstoreitintheIR o NotethattheaddressofthenextinstructiontobeexecutedisstoredinthePCregister o Proceedsinthefollowingmanner MAR PC(memoryaddressregisterisloadedwiththecontentofPC) PC ntedbyone) MDR interrogatememory,resultingintheinstructionbeing placedintheMDR) IR  o Fornow,wewillsaythateachofthesestepsproceedsinonemachinecycle o NotethattheinstructiontobeexecutedisnowstoredinIRandtheaddressofthenext instructiontobeexecutedisstoredinPC DECODEphase o TheinstructionstoredinPCisexaminedinordertodecidewhatportionofthe microarchitectureneedstobeinvolvedintheexecutionoftheinstruction o Forexample,fora4 ­bitopcode,thiscanbeimplementedasa4 ­to ­16decoder o Thisdecoderwillexaminebits12 ­15storedintheIRandwillactivatetheappropriate circuitrynecessarytocarryouttheinstruction EVALUATEADDRESSphase o Computetheaddressofthememorylocationthatisneededtoprocesstheinstruction o Someinstructionsdonotneedthisphase,e.g.,instructionsthatworkdirectlywiththe registersanddonotrequireanyoperandstobeloadedorstoredformmemory FETCHOPERANDSphase o Inthisphase,thesourceoperandsneededtocarryouttheinstructionareobtained frommemory o Forsomeinstructions,thisphaseequalstoloadingvaluesformtheregisterfile o Forothers,thisphaseinvolvesloadingoperandsfrommemory EXECUTEphase o Instructioniscarriedout  8 V.Kindratenko ECE190 Lecture08 February10,2011 o Someinstructionsmaynotrequirethisphase,e.g.,datamovementinstructionsfor whichalltheworkisactuallydoneintheFETCHOPERANDSphase STORERESULTSphase o Theresultiswrittentoitsdesignateddestination Afterthe6phasesoftheinstructioncyclearedone,thecontrolunitbeginsthenextinstruction cycle,startingwiththenewFETCH(instruction)phase o SincethePCwaspreviousincrementedbyone,itcontainsthepointertothenext instructiontobefetchedandexecuted Control of the instruction cycle Eachstepoftheinstructioncycleandofallitssub ­stepsiscontrolledbyaFSManabbreviated statediagramofwhichisshownbelow o Eachstatecorrespondstooneclockcycleofactivity o Theprocessingcontrolledbyeachstateisshownineachnode o Transitionbetweenstatesisshownbyarrows Instructioncyclestartswiththestate1andthenprogressestothenextstate State5 State1 Instruction1 MAR PC PC PC+1 State4 F E T CH State2 D E C OD E IR[15:12] MDR MEM[MAR] ... State3 StateM IR MDR Instructionn     9 V.Kindratenko ECE190 Lecture08 February10,2011 LC ­3 FSM Statemachineconsistsof52distinctstates o Shownonpage568(C.2)ofthetextbook   10 V.Kindratenko ...
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