lecture_09 - ECE190  ­ Lecture09...

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Unformatted text preview: ECE190  ­ Lecture09 February15,2011  ­ Lecture Topics LC ­3InstructionSetArchitecture LC ­3operateinstructions LC ­3datamovementinstructions Lecture materials Textbook§5.1 ­5.3 TextbookAppendixA.1 ­A.3 Homework HW2dueThursdayFebruary17at5pmintheECE190drop ­offbox HW3dueWednesdayFebruary23at5pmintheECE190drop ­offbox Machine problem MP1.2dueThursdayFebruary17at5pmsubmittedelectronically Announcements    1 V.Kindratenko ECE190 Lecture09 February15,2011 LC ­3 ISA ISA role ISAspecifiesalltheinformationaboutthecomputerthatthesoftwarehastobeawareof ISAdefinesaninterfacefortheprogrammerthatheneedstoknowwhenwritingprogramsin  SW InterfaceISA HW  ISAspecifiesthefollowing o Memoryorganization o Resisterset o Instructionset o Datatypes o Addressingmodels LC ­3 ISA overview Memoryorganization o 16 ­bitaddressable o 216addressspace 16 16 MDR data MAR 16 216 address 16 ... WE 16bits  2  V.Kindratenko ECE190 Lecture09 February15,2011 Registerset o 816 ­bitgeneral ­purposeregisters,namedR0 ­R7 Registerfile SR1 SR2 DR R0 R1 R2 R3 R4 R5 R6 R7 3 3 3 16 DRin 16 16 SR2out SR1out  o Otherspecial ­purposeregisters,suchasPCandIR Datatypes o 16 ­  Addressingmodels o Amechanismforspecifyingwheretheoperandsarelocated o Non ­memoryaddresses immediate(partoftheinstruction) register o Memoryaddresses PC ­relative,base+offset,indirect Theinstructionset o 16 ­bitinstructions o Bits12 ­15ofthe16 ­bitinstructionareusedtospecifytheopcode o Operateinstructions:ADD,AND,NOT o Datamovementinstructions:LD,LDI,LDR,LEA,ST,STR,STI o Controlinstructions:BR,JSR/JSSR,JMP,RTI,TRAP Conditioncodes o LC ­3has3single ­bitregistersthataresetto0or1eachtimeoneofthegeneral ­purpose registers(R0 ­R7)iswrittento N,Z,P conditioncodes N=1(Z=P=0)whenthevaluestoredinoneoftheregistersisnegative P=1(Z=N=0)whenthevaluestoredinoneoftheregistersispositive Z=1(N=P=0)whenthevaluestoredinoneoftheregistersiszero  3 V.Kindratenko ECE190 Lecture09 February15,2011 LC ­3 operate instructions NOT Operation:bitwisecomplementofthevaluefromthesourceregister(SR)isstoredinthe destinationregister(DR) o DR NOT(SR) o setcc   (modifiesconditioncodes) Encoding: 15 NOT 14 13 12 11 10 9 8 7 1001 opcode 6 5 4 3 2 1 0 111111 source register destination register unusedbits  Datapathrelevanttotheexecutionofthisinstruction: o Example:1001011101111111;NOTR3,R5 R0 R1 R2 R3 R4 R5 R6 R7 0100000011100101 1011111100011010 16 NOT 16 N=0 Z=0 P=1 ALU   4 V.Kindratenko ECE190 Lecture09 February15,2011 ADD (register mode) Operation:valuesfromtwosourceregisters(SR1andSR2)areaddedtogether( complementaddition)andtheresultingvalueisstoredinthedestinationregister(DR) o DR SR1+SR2 o setcc   (modifiesconditioncodes) Encoding: 15 ADD 14 13 12 11 10 9 8 7 6 0001 opcode 5 4 3 2 1 0 0 00 unusedbits source register1 addressingmode destination register source register2  Datapathrelevanttotheexecutionofthisinstruction: o Example:0001001010000110;ADDR1,R2,R6 R0 R1 R2 R3 R4 R5 R6 R7 0000000000010010 0000000000000011 0000000000001111 16 ADD 16 N=0 Z=0 P=1 ALU   5 V.Kindratenko ECE190 Lecture09 February15,2011 ADD (immediate mode) Operation:valuefromonesourceregister(SR1)isaddedtothesign ­extendedimm5filed(last5 bitsoftheinstruction)andtheresultingvalueisstoredinthedestinationregister(DR) o DR SR1+SEXT(imm5) o setcc   (modifiesconditioncodes) Encoding: 15 ADD 14 13 12 11 10 9 8 7 6 5 0001 opcode 4 3 2 1 0 1 5 ­bit2's source complement register1 number addressingmode destination register  Datapathrelevanttotheexecutionofthisinstruction: o Example:0001001100111110;ADDR1,R4,# ­2 3 0000000000000100 DR 3 0000000000000110 SR IR 0 0 0 1 0 0 1 1 0 0 1 1 1 1 1 0 5 R0 R1 R2 R3 R4 R5 R6 R7 16 S E XT 16 IR[5] 16 N=0 Z =0 P=1 ADD 16 ALU  imm5fieldis5 ­bitlong intervalfrom ­24to24 ­1( ­16..15)  6 V.Kindratenko ECE190 Lecture09 February15,2011 Few examples with ADD instruction Incrementvalueby1 o 0001110110100001;ADDR6,R6,#1 Decrementvalueby1: o 0001001001111111;ADDR6,R6,# ­1 Copyvaluefromoneregistertoanother o 0001110001100000;ADDR6,R1,#0  o o o o o WewanttocomputeA=B C ButthereisnosubtractioninstructioninLC ­3ISA! Wecanreplacesubtractionwithaddition:A=B+( ­C) AdditiveinverseofCcanbecomputedusingNOTandADDinstructions Thesubtractionprocedureis R1 B(loadvalueofBtoregister1) R2 C(loadvalueofCtoregister2) R2 NOT(R2)(computebitwisecomplementof2) R2 R2+1(addonetoget ­C) R3 R1+R2[A=B+( ­C)] Theprogram(inLC ­3machinelanguage!): 1001010010111111  0001010010100001  0001011001000010  o       ;R2 NOT(R2) ;R2 R2+1 ;R3 R1+R2 Thereisonefundamentalflawwiththisprogram:valuestoredinregister2willbe modifiedintheprocessofprogramexecution(whatifweneedvalueofClateron?) Abetterwayistostoreintermediatevalueinanother(unused)register About notation Machinecodelookslikethis:1001010010111111 o Forourconvenience,ONPAPERwecanseparatethe16bitsthatmakeupaninstruction intosmallergroupsbasedontheirmeaning,e.g.:1001010010111111 Wecanalsoaddacommenttoalineofbinarycodeusingsemicolontoseparateitfromthe actualinstruction,e.g.,1001010010111111;somecommentgoeshere Wecanusethreestylesofcomments o Words,e.g.:addnumbersfromR1andR2andplacetheresultstoR3 o Registertransferstyle,e.g.:R3 R1+R2 o Assemblycodestyle,e.g.:ADDR3,R1,R2 Whicheverstyleyoudecidetouse,justbeconsistent!    7 V.Kindratenko ECE190 Lecture09 February15,2011 AND (register mode) resultingvalueisstoredinthedestinationregister(DR) o DR SR1ANDSR2 o setcc   (modifiesconditioncodes) Encoding: 15 AND 14 13 12 11 10 9 8 7 6 0101 4 3 2 1 0 0 00 unusedbits source register1 addressingmode destination register opcode 5 source register2  DatapathrelevanttotheexecutionofthisinstructionisidenticaltotheregistermodeADD instruction,theonlydifferenceistheselectsignaltotheALU Example:0101001010000111;ANDR1,R2,R7 AND (immediate mode)  ­extendedimm5filed (last5bitsoftheinstruction)andtheresultingvalueisstoredinthedestinationregister(DR) o DR SR1ANDSEXT(imm5) o setcc   (modifiesconditioncodes) Encoding: 15 AND 14 13 12 11 10 9 8 0101 6 5 4 3 2 1 0 1 source 5 ­bitbitfield register1 addressingmode destination register opcode 7  DatapathrelevanttotheexecutionofthisinstructionisidenticaltotheregistermodeADD instruction,theonlydifferenceistheselectsignaltotheALU Example:0101001010100001;ANDR1,R2,#1   8 V.Kindratenko ECE190 Lecture09 February15,2011 Few examples with AND instruction Clearregister o 0101110110100000;R6 R6ANDSEXT(00000) Copyvaluefromoneregistertoanother o 0101110000111111;R6 R1ANDSEXT(11111) ImplementbitwiseORoperation o WewanttocomputeA=BORC o ButthereisnoORinstructioninLC ­3ISA! o o Theprocedureis R1 B(loadvalueofBtoregister1) R2 C(loadvalueofCtoregister2) R1 NOT(R1) R2 NOT(R2) R3 R1ANDR2 R3 NOT(R3)  LC ­3 data movement instructions Load effective address instruction (LEA) Operation:loadthedestinationregister(DR)withthevalueformedbyaddingvaluesfromPC registerandthesign ­extendedlast9bitsoftheinstruction(PCoffset9) o DR PC+SEXT(PCoffset9) o setcc Implementsimmediateaddressingmode o Operandtobeloadedtodestinationregisterisobtainedimmediately,withoutany accesstomemory Encoding: 15 L EA 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1110 opcode destination register PCoffset9  Datapathrelevanttotheexecutionofthisinstruction: o Example:1110101111111101;LEAR5,offset  9 V.Kindratenko ECE190 Lecture09 February15,2011 R0 R1 DR R2 R3 R4 R5 R6 R7  ­3 IR 1 1 1 0 1 0 1 1 1 1 1 1 1 1 0 1 9 x4019 3 x4016 IR[8:0] PC 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 1 S E XT 16 16 ADD NZP 16 x4016 001  R5 PC+SEXT(IR[8:0]) UsefulforloadinganaddressofmemorytobelateronusedwithLDR/STRinstructions    10 V.Kindratenko ...
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This note was uploaded on 01/22/2012 for the course ECE 191 taught by Professor Staff during the Spring '11 term at University of Illinois, Urbana Champaign.

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