lecture_10 - ECE190  ­ Lecture10...

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Unformatted text preview: ECE190  ­ Lecture10 February17,2011  ­ Lecture Topics LC ­3datamovementinstructions LC ­3controlinstructions Example Lecture materials Textbook§5.3 ­5.6 TextbookAppendixA.3 Homework HW3dueWednesdayFebruary23at5pmintheECE190drop ­offbox Machine problem MP2dueMarch2,2011at5pmsubmittedelectronically. Announcements    1 V.Kindratenko ECE190 Lecture10 February17,2011 LC ­3 data movement instructions Overview Load:movedatafrommemorytoregister o LD,LDI,LDR o LEA immediatemodeloadinstruction Store: o ST,STR,STI Load/storeinstructionformat 15 14 13 12 11 10 9 8 7 destination orsource register opcode 6 5 4 3 2 1 0 addressgenerationbits  4waystointerpretaddressgenerationbits(4addressingmodes) o PC ­relevantmode(LDandSTinstructions) o Indirectmode(LDIandSTIinstructions) o Base+offsetmode(LDRandSTRinstructions) o Immediatemode(LEAinstruction) Load instruction using base + offset addressing mode (LDR) Operation:thecontentofmemoryattheaddresscomputedasthesumoftheaddressstoredin thebaseaddressregister(BaseR)andthesign ­extendedlast6bitsoftheinstruction(offset6)is loadedintothedestinationregister(DR) o DR mem[BaseR+SEXT(offset6)] o setcc Encoding: 15 L DR 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0110 opcode destination register baseaddress register offset6  Datapathrelevanttotheexecutionofthisinstruction: o Example:0110001010011101;LDRR1,R2,offset  2 V.Kindratenko ECE190 Lecture10 February17,2011 3 DR BaseR R0 R1 xABCD x2345 3 R2 R3 R4 R5 R6 R7 x1D IR 0 1 1 0 0 0 1 0 1 0 0 1 1 1 0 1 IR[5:0] 6 S E XT 16 ADD NZP x2362 16 16 100 MAR x2362 MDR xABCD  MAR R2+SEXT(IR[5:0]) MDR mem[MAR] R1  offset6fieldis6 ­bitwide,thustheoffsetcanbefrom ­32to+31 Store instruction using base + offset addressing mode (STR) Operation:valuestoredinthesourceregister(SR)istransferredtothememoryattheaddress computedasthesumoftheaddressstoredinthebaseaddressregister(BaseR)andthesign ­ extendedlast6bitsoftheinstruction(offset6) o mem[BaseR+SEXT(offset9)]  Encoding: 15 S TR 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0111 opcode source register baseaddress register offset6  Datapathrelevanttotheexecutionofthisinstruction: o Example:0111001010011101;STRR1,R2,offset  3 V.Kindratenko ECE190 Lecture10 February17,2011 3 SR BaseR R0 R1 xF E D C x2345 3 R2 R3 R4 R5 R6 R7 x1D IR 0 1 1 1 0 0 1 0 1 0 0 1 1 1 0 1 IR[5:0] 6 S E XT 16 ADD x2362 16 16 MAR MDR x2362 xF E D C  MAR R2+SEXT(IR[5:0]) MDR R1 mem[MAR]  Load instruction using PC relative addressing mode (LD) Operation:thecontentofmemoryattheaddresscomputedasthesumoftheaddressstoredin PCregisterandthesign ­extendedlast9bitsoftheinstruction(PCoffset9)isloadedintothe destinationregister(DR) o DR mem[PC+SEXT(PCoffset9)] o setcc Encoding: 15 LD 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0010 opcode destination register PCoffset9  Datapathrelevanttotheexecutionofthisinstruction: o Example:0010000110101111;LDR0,offset  4 V.Kindratenko ECE190 Lecture10 February17,2011 3 DR 0011001100110011 R0 R1 x1AF R2 R3 R4 R5 R6 R7 IR 0 0 1 0 0 0 0 1 1 0 1 0 1 1 1 1 9 IR[8:0] x4018 PC 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 1 S E XT 16 16 NZP ADD 001 16 x3FC8 16 MAR x3FC8 MDR 0011001100110011  MAR PC+SEXT(IR[8:0]) MDR mem[MAR] R0  Store instruction using PC relative addressing mode (ST) Operation:valuestoredinthesourceregister(SR)istransferredtothememoryattheaddress computedasthesumoftheaddressstoredinPCregisterandthesign ­extendedlast9bitsof theinstruction(PCoffset9) o mem[PC+SEXT(PCoffset9)]  Encoding: 15 ST 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0011 opcode source register PCoffset9  Datapathrelevanttotheexecutionofthisinstruction: o Example:0011000110101111;STR0,offset  5 V.Kindratenko ECE190 Lecture10 February17,2011 3 SR 1111111111110000 R0 R1 x1AF R2 R3 R4 R5 R6 R7 IR 0 0 1 1 0 0 0 1 1 0 1 0 1 1 1 1 9 IR[8:0] x4018 PC 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 1 S E XT 16 16 ADD 16 x3FC8 16 MAR x3FC8 MDR 1111111111110000  MAR PC+SEXT(IR[8:0]) MDR R0 mem[MAR]  PCoffset9fieldis9 ­bitwide,thustheoffsetcanbefrom ­256to+255 Load instruction using indirect addressing mode (LDI) Operation:thecontentofmemoryattheaddressstoredinmemoryattheaddresscomputedas thesumoftheaddressstoredinPCregisterandthesign ­extendedlast9bitsoftheinstruction (PCoffset9)isloadedintothedestinationregister(DR) o DR mem[mem[PC+SEXT(PCoffset9)]] o setcc Encoding: 15 L DI 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1010 opcode destination register PCoffset9  Datapathrelevanttotheexecutionofthisinstruction:  6 V.Kindratenko ECE190 Lecture10 o February17,2011 Example:1010011111001100;LDIR3,offset DR x1CC R0 R1 IR 1 0 1 0 0 1 1 1 1 1 0 0 1 1 0 0 3 9 R2 R3 R4 R5 R6 R7 xF F F F IR[8:0] x4A1C PC 0 1 0 0 1 0 1 0 0 0 0 1 1 1 0 0 S E XT 16 16 ADD NZP 16 x49E8 16 100 MAR MDR x2110 xF F F F x49E8 x2110  MAR PC+SEXT(IR[8:0]) MDR mem[MAR] MAR  MDR  R3  Store instruction using indirect addressing mode (STI) Operation:valuefromthesourceregister(SR)istransferredtothememoryattheaddress storedinmemoryattheaddresscomputedasthesumoftheaddressstoredinPCregisterand thesign ­extendedlast9bitsoftheinstruction(PCoffset9) o mem[mem[PC+SEXT(PCoffset9)]] SR Encoding: 15 S TI 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1011 opcode source register PCoffset9  Datapathrelevanttotheexecutionofthisinstruction: o Example:1011011111001100;STIR3,offset  7 V.Kindratenko ECE190 Lecture10 February17,2011 SR x1CC R0 R1 IR 1 0 1 1 0 1 1 1 1 1 0 0 1 1 0 0 3 9 xAAAA IR[8:0] x4A1C PC 0 1 0 0 1 0 1 0 0 0 0 1 1 1 0 0 S E XT 16 R2 R3 R4 R5 R6 R7 16 ADD 16 x49E8 16 MAR MDR x2110 xAAAA x49E8 x2110  MAR PC+SEXT(IR[8:0]) MDR mem[MAR] MAR  MDR  MDR LC ­3 control instructions Controlinstructionschangethesequenceoftheinstructionsthatareexecuted.Theachievethis bydirectlymanipulatingthevalueofPCregister. ControlinstructionssupportedbyLC ­3 o JMP ­unconditionaljump o BR conditionalbranch o TRAP invokesanOSservicecall o JSR/JSRR subroutinecall o RET returnfromsubroutine o RTI returnfrominterrupt FornowwewillstudyonlyJMP,BR,andTRAPinstructions Conditional branches (BR) Operation:ifanyoftheconditioncodestestedisset,incrementthePCwiththesign ­extended PCoffset9(bits0 ­8oftheinstruction).Inotherwords,branchistakenifspecifiedconditionis true.  8 V.Kindratenko ECE190 Lecture10 February17,2011 o If(nANDN)OR(zANDZ)OR(pANDP))thenPC Encoding: 15 14 13 12 11 10 9 8 7 PC+SEXT(PCoffset9) 6 5 4 3 2 1 0 0000nzp BR opcode condition codestotest PCoffset9  PCoffsetrangeisfrom (2)8to28 ­1 Datapathrelevanttotheexecutionofthisinstruction: PC +1 N 1 PCMUX P Z #0#1 IR 0 0 0 0 n z p 9 IR[8:0] ADD S E XT 16 16  InstructioncycleforBR: o FETCHANDDECODEphasesarethesameasforanyotherinstruction NotethatPC  o EVALUATEADDRESSphase:computePC+SEXT(PCoffset9) o EXECUTEphase ConditioncodesN,Z,Pforwhichcorrespondingbitsn,z,paresetinthe instructionareexamined,.e.g., Ifn=1,Nconditioncodeinschecked  9 V.Kindratenko ECE190 Lecture10 February17,2011 Iftheconditioncodethatwasexaminedisset,thebranchistaken,thatis  Otherwise,  Ifall3bitsn,z,poftheinstructionareset,thenall3conditioncodesN,Z,Pare examined,andsinceatleastoneofthemmustbeset,theconditionisalways met,andthebranchisalwaystaken,essentiallyunconditionally. Example1: o Z=1,N=P=0 o PC:x4027 o IR:0000010011011001;BRz,x0D9 o x4101) Example2: o ForanyN,Z,P o PC:x507B o IR:0000111110000101;BRnzp,x185 o x5001) Example3: o N=1,Z=P=0 o PC:x3000 o IR:0000100111111111;BRz.# ­1 o  ­#1( x3000) Unconditional jump (JMP) Operation:loadthePCwiththecontentsoftheregisterspecifiedbybits6 ­8 o PC BaseR Encoding: 15 JMP 14 13 12 11 10 9 8 7 1100 000 6 5 4 3 2 1 0 000000 opcode BaseR  Datapathrelevanttotheexecutionofthisinstruction: o Example:1100000111000000;JMPR7  10 V.Kindratenko ECE190 Lecture10 February17,2011 R0 R1 BaseR R2 R3 R4 IR 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 R5 R6 3 x4000 x4000 R7 PC 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0  JMPinstructionhasnolimitationsonwherethenextinstructiontobeexecutedislocatedsince thefull16 ­bitmemoryaddresscanbestoredintheregister. TRAP Operation:changesPCtoamemoryaddressthatisapartoftheOS.Astheresult,OSgets controlanexecutessometaskonbehalfofourprogram o PC trapvector] Encoding: 15 TRAP 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1111 0000 opcode unused trapvector  TRAPinstructioninvokesanoperatingsystemservicecallidentifiedbybits7:0oftheinstruction Fornow,rememberthefollowing3trapvectors: o x23allowstoinputacharacterfromthekeyboard,itsvaluewillbeplacedinR0 o x21allowstooutputacharactertothedisplay(R0[7:0]arewrittenout) o x25haltstheprogram wewilllookattheimplementationdetailsofTRAPinstructionlater(Ch9) Multiplication example Writeaprogramthatcomputesaproductoftwointegers:axb=p aandb  wewillimposearestrictionthatb>0 algorithm:replaceproductwiththesum:p=a+a+..+a(btimes) o wewilluseR0toholdvalueofa  11 V.Kindratenko ECE190 Lecture10 February17,2011 o o o o wewilluseR1toholdvalueofb wewilluseR2toholdvalueofp ourprogramwillbelocatedinmemorystartingattheaddressx3000 beforetheprogramstarts valueofaislocatedinmemoryattheaddressx3010 valueofbislocatedinmemoryattheaddressx3011 o whentheprogramisdone,valueofpshouldbelocatedinmemoryattheaddressx3012 First,werepresentthealgorithmforsolvingourproblemasaflowchart  start addr x3000 x3001 x3002 x3003 x3004 x3005 x3006 x3007 x3008 x3009 x300A x300B x300C x300D x300E x300F x3010 x3011 x3012  Initialize:  ­getvaluesofaand bfrommemory  ­clearvalueofp p=p+a no havewedoneitb times? yes storevalueofpin memory stop binaryinstruction 0101010010000000 0010000000001110 0010001000001110 0001010010000000 0001001001111111 0000001111111101 0011010000001011 1111000000100101             comments R2 0(AND,R0,R0,#0) R0 a(LD,R0,#14) R1 b(LD,R1,#14) R2 R2+R0(ADDR2,R2,R0) R1 R1 ­1(ADDR1,R1,# ­1) PC x3003(BRp,# ­3) p R2(STR2,#11) HALT         aisstoredhere bisstoredhere pistobestoredhere    Next,wetranslatetheflowchart,stepbystep,intoaprograminmachinelanguage o Wesavetheprogram(binaryinstructioncolumnandoptionallycommentscolumn only!)intoafinewithextension.bin,e.g.,mult.bin o Alsoneedtoaddalineofcodethatspecifiesthestartingaddressoftheprogram o ConvertittoanLC ­3executable:lc3convertmult.bin o UseeithercommandlineorgraphicalLC ­3simulatortorunit commandlineLC ­3simulator:lc3simmult.obj graphicalLC ­3simulator:lc3sim ­tkmult.obj  12 V.Kindratenko ...
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This note was uploaded on 01/22/2012 for the course ECE 191 taught by Professor Staff during the Spring '11 term at University of Illinois, Urbana Champaign.

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