EE2731_Lab2report

EE2731_Lab2report - and a single inverter, design and build...

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Heath J LeBlanc Mariel Losso 9/27/05 EE 2731 Section 3, Group 5 Experiment 2 – Decoders, Multiplexers, and Demultiplexers
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Two-to-Four Binary Decoder with Enable Part A: a) Design and build a 2 to 4 binary decoder with an enable. The truth table for this device is given below. A and B are the inputs and Y 0 ’, Y 1 ’, Y 2 ’, and Y 3 ’ are the outputs. Digital Inputs: Data Inputs: EN’, A, and B from switches Select Lines: None. Clock: None. Digital Output: Y 0 ’, Y 1 ’, Y 2 ’, and Y 3 EN’ A B Y 0 Y 1 Y 2 Y 3 1 X X 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 1 1 0 1 0 1 1 0 1 0 1 1 1 1 1 0 Equations from Truth Table: Y 0 = EN’ A’ B’ Y 1 = EN’ A’ B Y 2 = EN’ A B’ Y 3 = EN’ A B So that Y 0 ’ = (EN’ A’ B’)’ Y 1 ’ = (EN’ A’ B)’ Y 2 ’ = (EN’ A B’)’ Y 3 ’ = (EN’ A B)’
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Logic Diagram: Control Inputs: None Power Inputs: Supply Pin#14 Chip# 74LS- 04, 10 (D1), 10 (D2) Ground Pin#7 Chip# 74LS- 04, 10 (D1), 10 (D2) Part B: b) Using the decoder you designed in experiment part (a), a 2 to 4 decoder from a 74LS139,
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Unformatted text preview: and a single inverter, design and build a 3 to 8 decoder. Digital Inputs: Data Inputs: A, B, and C from switches Select Lines: None. Clock: None. Digital Output: Y , Y 1 , Y 2 , Y 3 , Y 4 , Y 5 , Y 6 , and Y 7 To design this circuit, we can just connect the input, C, to EN_L input of our circuit from Part A, and connected the inverted C input, C, to the Enable of the 2-to-4 decoder of the 74LS139. Also, connecting inputs A and B to the least significant and most significant inputs, respectively, of the 74LS139 will yield the following design. Logic Diagram: Control Inputs: None Power Inputs: Supply Pin#14 Chip# 74LS- 04, 10 (D1), 10 (D2) Pin#16 Chip# 74LS139 Ground Pin#7 Chip# 74LS- 04, 10 (D1), 10 (D2) Pin#8 Chip# 74LS139...
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This note was uploaded on 01/23/2012 for the course EE 2731 taught by Professor Audiferred during the Fall '11 term at LSU.

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EE2731_Lab2report - and a single inverter, design and build...

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