Lab Report 4

Lab Report 4 - Jonathan Bollinger Randall Robert Experiment...

Info iconThis preview shows pages 1–4. Sign up to view the full content.

View Full Document Right Arrow Icon
Jonathan Bollinger Randall Robert Experiment 4 – Flip-Flops Part A: Construct A SR latch with two NAND gates. Digital Inputs: A 1 and S 2 B . Select Lines – None C . Clock – None Digital Outputs: Truth Table: Karnaugh Map: none Equations: Characteristic Eq. Q* = R’Q+S Logic Diagram: 0 S 0 R U1A U1B -2,? Q -2,? QN A. Pin Numbers – 1 = S 2,6= QN 3,4 = Q 5 = R S R Q QN 0 0 Last Q Last QN 0 1 0 1 1 0 1 0 1 1 0 0 1
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
B. All gates belong to one 74ls00 Lab 4a-Trace 0 1 2 3 4 In1 0 1 In2 0 1 Out1 0 1 Out2 0 1 ? S ? S Control Inputs: None Power Inputs: |||||||||||||||||| Pin # Chip # Supply 14 74ls00 Ground 7 74ls00 Part B: Construct a D latch by modifying part a. Digital Inputs: A . Data Inputs – D from S 1 B . Select Lines – none C . Clock – More like an enable = C Digital Outputs: Truth Table: Karnaugh Map: not necessary Equations: D=Q* Logic Diagram: C D Q QN 1 0 0 1 1 1 1 0 0 X Last Q Last QN 2
Background image of page 2
-2,? Q
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 4
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 01/23/2012 for the course EE 2731 taught by Professor Audiferred during the Fall '11 term at LSU.

Page1 / 9

Lab Report 4 - Jonathan Bollinger Randall Robert Experiment...

This preview shows document pages 1 - 4. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online