This preview has intentionally blurred sections. Sign up to view the full version.View Full Document
Unformatted text preview: Truth Table: SO S1 O0* O1* O2* O3* I0 I1 I2 I3 1 1 O0 O1 O2 1 O1 O2 O3 O0 1 1 O0’ O1’ O2’ O3’ Karnaugh Maps: None Equations: None Logic Diagram: Control Inputs: clock Power Inputs: Supply Pin # 14 Chip # 74LS –74 Ground pin # 7 Chip # 74LS –74 Supply Pin # 16 Chip # 74LS –153 Ground pin # 8 Chip # 74LS – 153...
View Full Document
This note was uploaded on 01/23/2012 for the course EE 2731 taught by Professor Audiferred during the Fall '11 term at LSU.
- Fall '11