Lab Report 1

Lab Report 1 - Select Lines None Clock None Digital Outputs...

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Jonathan Bollinger Randall Robert Experiment 1 - Combinational Logic Circuits Part A: Design and build a 4-input majority circuit using AND, OR, and NOT gates. Digital Inputs: Data Inputs: Select Lines: None Clock: None Digital Outputs: Z Truth Table: A B C D Z 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 1 1 1 0 0 0 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1 Karnaugh Maps: None needed since output equation is easily derived from truth table. Equations: Z = BCD + ACD + ABD + ABC + ABCD Z = CD(A+B) + AB(C+D) Logic Diagram: Control Inputs: None
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Power Inputs: Supply Pin # 14 Chip # 74LS - 11, 32 Ground Pin # 7 Chip # 74LS - 11, 32 Trace: Attached to back of lab report. Ouptut Table: Attached to back of lab report. Part B: Repeat A and this time design the circuit using NAND gates only. Also, use the least number of gates you possibly can. Digital Inputs: Data Inputs:
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Unformatted text preview: Select Lines: None Clock: None Digital Outputs: Z Truth Table: A B C D Z 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Karnaugh Maps: None used to derive equations. Equations: Z = [ (BCD)' (ACD)' (ABD)' (ABC)']' Logic Diagram: Control Inputs: None Power Inputs: Supply Pin # 14 Chip # 74LS - 10, 20 Ground Pin # 7 Chip # 74LS - 10, 20 Trace: Trace for circuit B is same as the the trace for circuit A, which is attached. Ouptut Table: Table for circuit B is same as the the trace for circuit A, which is attached....
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Lab Report 1 - Select Lines None Clock None Digital Outputs...

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