Lab Report 6

Lab Report 6 - A4A d clk A3B vcc In6 In5 In4 ns 10000n U1-2 Out3-2 Out4-2 Out5 In3 A B-2 Out6-2 Out7-2 Out8-2 Out9 vcc Timing Diagram 2 Control

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Jonathan Bollinger Randall Robert Experiment 6 – Shift Registers Part A: Design and build a 4-bit shift register with four D flip-flops and four 4-1 multiplexers. This circuit should be capable of performing the following functions: Mode Control: S0 S1 Register Operation 0 0 Parallel Load 0 1 Shift Right 1 0 Rotate Left 1 1 Complement Truth/Function Table: For 74ls74: For 74ls153: 1
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Karnaugh Map: None used. Equations : None used. Logic/Circuit Diagram: en 0 1 2 3 mux 0 1 A1A g 0 3 en 0 1 2 3 mux 0 1 A2A g 0 3 -2,? Out2 d clk A5A d clk A4B d clk
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Unformatted text preview: A4A d clk A3B vcc In6 In5 In4 ns 10000n U1-2,? Out3-2,? Out4-2,? Out5 In3 A B-2,? Out6-2,? Out7-2,? Out8-2,? Out9 vcc Timing Diagram: 2 Control Inputs: A & B, pins 2 & 14, of chips 74153 Strobe: pins 1 & 15 of chips 74153 Preset: pins 4 & 10 of chips 7474 Clear: pins 1 &13 of chips 7474 Reset: none Power Inputs: ||||||||||||||||||||||||| 74LS74 74LS153 Vcc Pin 14 Pin16 Ground Pin 7 Pin 8 3...
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This note was uploaded on 01/23/2012 for the course EE 2731 taught by Professor Audiferred during the Fall '11 term at LSU.

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Lab Report 6 - A4A d clk A3B vcc In6 In5 In4 ns 10000n U1-2 Out3-2 Out4-2 Out5 In3 A B-2 Out6-2 Out7-2 Out8-2 Out9 vcc Timing Diagram 2 Control

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