Lab Report 8

Lab Report 8 - Input 00100011100101 Output 00001000010011...

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Jonathan Bollinger Randall Robert Experiment 8 – Sequence Detector Part B: Design a sequential logic circuit to check an input stream labeled X and to produce an output Z=1 if the total number of zeros received is odd and the sequence 10 has occurred at least once. The total number of zeros received include before, during and after the sequence 10 is received. Make sure your circuit has a start state and the means to manually reset the flip-flops to the start state. Note that the circuit does not reset to the start state when an output Z=1 occurs. Testing your circuit will involve checking the correctness of every state and next state for all possible combination of inputs.
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Unformatted text preview: Input: 00100011100101 Output: 00001000010011 Truth/Function Table: For 74ls74: For 74ls74: Karnaugh Map: None used. Equations : None used. Logic/Circuit Diagram: 1 Input 1 Reset Out1 j ck k A1 j ck k A2 A1A vcc A1B d clk U1A ns 10m U2 Timing Diagram: Lab 8b-Trace 20 40 60 80 100 120 140 160 180 200 Input 1 Reset 1 Out1 1 U2 1 ? X ? S Control Inputs: none Strobe: none Preset: pins 4 & 10 of chips 7474 Clear: pins 1 &13 of chips 7474 Reset: none Power Inputs: ||||||||||||||||||||||||| 74LS74 74LS76 74LS02 Vcc Pin 14 Pin5 Pin14 Ground Pin 7 Pin 13 Pin7...
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Lab Report 8 - Input 00100011100101 Output 00001000010011...

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