6 - HW Schemes for ILP

6 - HW Schemes for ILP - HW Schemes for ILP Speculation-...

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Unformatted text preview: HW Schemes for ILP Speculation- Memory access Limits to Multi-Issue Machines Inherent limitations of ILP 1 branch in 5: How to keep a 5-way VLIW busy? Latencies of units: many operations must be scheduled Need about Pipeline Depth x No. Functional Units of independent operations to keep machines busy, e.g. 5 x 4 = 15 20 independent instructions? Difficulties in building HW Easy: More instruction bandwidth Easy: Duplicate FUs to get parallel execution Hard: Increase ports to Register File (bandwidth) VLIW example needs 7 read and 3 write for Int. Reg. & 5 read and 3 write for FP reg Harder: Increase ports to memory (bandwidth) Decoding Superscalar and impact on clock rate, pipeline depth? Limits to Multi-Issue Machines Limitations specific to either Superscalar or VLIW implementation Decode issue in Superscalar: how wide practical? VLIW code size: unroll loops + wasted fields in VLIW IA-64 compresses dependent instructions, but still larger...
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6 - HW Schemes for ILP - HW Schemes for ILP Speculation-...

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