03_architecture - Architecture Refresher Basic computer...

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&&rchitecture Refresher
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Basic computer structure &78 <= 4LMPRU \ PLMPRU\ IJXV 0!6 IJXV KLQV N 5LMW QQWLMUMNHIJKLM
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Memory Hierarchy Fpu FDFKH mDLn mHmory ZRUKL WUHIQVMNLMU IJORJKN WUHIQVMNLMU GLsN s SHIOLM WUHIQVMNLMU ● decrease cost per bit ● decrease frequency of access ● increase capacity ● increase access time ● increase size of transfer unit
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Memory Access Costs ● &&M)) &&thlon !° X± ±²²³ [http%´´wwwµdigit¶lifeµcom´articles±´cpu´rmma¶a!°x±¶ee¶page·µhtml] ○ L·% ¸ cycles¹ ·±#K'' I³))¹ ±¶way¹ !° bytes lines ○ L±% ·" cycles¹ ·±K'' unified¹ ·!¶way¹ !° bytes lines ○ Memory% #µ#¶##ns ºseqµ´random»% ±¸¶±¸² cycles %% ±µ!,G-Hz
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Memory Caches ● Motivated by the mismatch between processor and memory speed ● Closer to the processor than the main memory ● Smaller and faster than the main memory ● Act as ±attraction memory±: contains the value of main memory locations which were recently accessed ²temporal locality³
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