03_architecture - Architecture Refresher Basic computer...

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&rchitecture Refresher
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Basic computer structure = 4MPRU \ PMPRU\ JXV 0!6 JXV LQV N 5MW QqWMUnIKM
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Memory Hierarchy Fpu FDFKH mDLn mHmory ZRUL WUIQVNMU JORKn WUIQVNMU GLsN s SIoM WUIQVNMU ● decrease cost per bit ● decrease frequency of access ● increase capacity ● increase access time ● increase size of transfer unit
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Memory Access Costs [http·¸¸www¹digitºlife¹com¸articles³¸cpu¸rmmaºa±²x³ºeeºpage»¹html] ○ L»· ¼ cycles½ »³¾K' I¶)½ ³ºway½ ±² bytes lines ○ L³· »¿ cycles½ ´»³K' unified½ »±ºway½ ±² bytes lines ○ Memory· ¾¹¾º¾¾ns Àseq¹¸randomÁ· ³¼º³¼µ cycles % ³¹±GHz
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Memory Caches ● Motivated by the mismatch between processor and memory speed ● Closer to the processor than the main memory ● Smaller and faster than the main memory ● Act as ±attraction memory±: contains the value of main memory locations which were recently accessed ²temporal locality³ ● Transfer between caches and main memory is performed in
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This note was uploaded on 01/22/2012 for the course COMPUTER S 302 taught by Professor Stewart during the Spring '11 term at N.C. State.

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03_architecture - Architecture Refresher Basic computer...

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