20091eeM16_3_hw2

20091eeM16_3_hw2 - minimize the number of NAND gates in...

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EEM 16 HOMEWORK #2 Winter 2009 Due on Wed, January 21 st , 2009 1. Exercise 2.43 (a) 2. Exercise 3.2, and re-draw the correct CMOS schematic for z=(a +b )c d . 3. Exercise 3.9 4. Exercise 3.11 5. Design a 2-input Exclusive-OR (XOR) gate using only 2-input NAND gates. Try to
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Unformatted text preview: minimize the number of NAND gates in your design. 6. (a) Construct the truth table for the following circuit. (b) Write the logic expression for circuit shown in (a). (c) Convert the truth table in (a) into K-map and find all PIs and EPIs....
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20091eeM16_3_hw2 - minimize the number of NAND gates in...

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