20091eeM16_3_hw5

20091eeM16_3_hw5 - b) Implement the counter using D flip...

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EEM 16 HOMEWORK #5 Winter 2009 Due on Wed, February 11 th , 2009 1. Exercise 8.2 Note: Timing factors include network setup time, network hold time, network propagation delay, minimum clock period and maximum clock frequency. 2. Design a counter with one-bit control input. When the input is high, the counter should sequence through three states: 10, 01, 11 and repeat. When the input is low the counter should sequence through the same states in the opposite order 11, 01, 10 and repeat. a) Draw the state diagram and state transition table
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Unformatted text preview: b) Implement the counter using D flip flops and whatever gates you like. 3. Exercise 8.13 Note: Assume you must always input 4 digits at a time in sequence. For example, let s say you enter in 1 st digit correctly. Then you make a mistake when entering the 2 nd digit. You must enter the 3 rd and 4 th digit as well. You cannot reset or start over after only entering 2 digits. 4. Exercise 8.22 5. Obtain the state diagram of the sequential network show below....
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This note was uploaded on 01/24/2012 for the course EE M16 taught by Professor Cabric during the Fall '08 term at UCLA.

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