Unformatted text preview: implement full adder. 2. Exercise 9.10 3. Design a 3-bit odd parity decoder module (OPD). OPD gets three inputs a , b and c and computes the odd parity bit p . is set to one if the number of 1s in the input is odd and is set to 0 if the number of 1s is even. Design this module using only one 8-to-1 multiplexer with no additional logic. 4. Exercise 9.24 5. Exercise 10.10...
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- Fall '08
- Gate, Parity bit, odd parity, odd parity bit, odd parity decoder