20091eeM16_3_hw6

20091eeM16_3_hw6 - implement full adder 2 Exercise 9.10 3...

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EEM 16 HOMEWORK #6 Winter 2009 Due on Wed, February 18 th , 2009 1. Using only JK Flip-flops and NAND gates to design a sequential network that outputs 1 if at least 4 of the last 7 input bits were 1. Otherwise the output is 0. The output is only one bit and the input is a bit stream with one bit arrived per clock cycle. You should optimize your circuit to minimize the numbers of flip-flops and gates used. Hint: Use JK flip-flop and NAND gate to implement D flip-flop and use NAND gates to
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Unformatted text preview: implement full adder. 2. Exercise 9.10 3. Design a 3-bit odd parity decoder module (OPD). OPD gets three inputs a , b and c and computes the odd parity bit p . is set to one if the number of 1s in the input is odd and is set to 0 if the number of 1s is even. Design this module using only one 8-to-1 multiplexer with no additional logic. 4. Exercise 9.24 5. Exercise 10.10...
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