M16_2_EEM16_F08_L05

M16_2_EEM16_F08_L05 - EEM16/CSM51A:...

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EEM16/CSM51A: Logic Design of Digital Systems Lecture #5 Ch 3: Combinational Integrated Circuits Ch 4: Description of Gate Networks Prof. Danijela Cabric Fall 2008
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Announcements ± HW#1 is due today by the end of the lecture ± HW#2 is posted on eeweb, due on Oct. 16 in class ± Lecture handouts are posted on eeweb ± Reading assignments Ch. 2,3 and 4 2
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Agenda ± Basic switch structure of gates and their operation ± Realization of gates using CMOS circuits ± Characteristics of circuits: load factors and fan out factors, propagation delays, transition times, and effect of load ± Three state gates (drivers) and buses ± Gate networks 3
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Electronic Switches are Basis of Binary Digital Circuits 4 A switch has three ports: Source Input : current enters here Output : current leaves here Control Input : voltage that control whether current can flow from Source Input to Output
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NMOS and PMOS Transistors 5
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A CMOS “NOT” Gate (Inverter) 6
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NAND Gate 7
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NOR Gate 8
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AND and OR Gates 9
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Complex Gates > Discussion on Friday 10
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Complex Gates > Discussion on Friday 11
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Transmission Gate 12
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XOR using Transmission Gates 13
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M16_2_EEM16_F08_L05 - EEM16/CSM51A:...

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