M16_2_EEM16_F08_L06

M16_2_EEM16_F08_L06 - EEM16/CSM51A Logic Design of Digital...

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Unformatted text preview: EEM16/CSM51A: Logic Design of Digital Systems Lecture #6 h 4: Description and Analysis of Gate Networks Ch 5: Design of Gate Networks Prof. Danijela Cabric Fall 2008 Announcements ¡ Reading assignments Chapters 4 and 5 ¡ Download and install Xilinx ISE webpack ¡ Instructions are posted on Eeweb ¡ Discussion on Friday will go over basic examples ¡ HW#3 includes the simulation of combinational design using Xilinx ISE 2 Agenda ¡ Gate networks ¡ Universal sets of gates ¡ Analysis and description of gate networks ¡ Design of two ‐ level networks ¡ Minimal two ‐ level networks ¡ Karnaugh maps ¡ Minimization procedure 3 Clarification: Transmission Gates 4 Gate Network 5 Gates Connections or Nets External inputs External outputs Gate Networks 6 Describing Gate Networks 7 Net List: Tabular Description of Gate Networks 8 Hardware Description Language 9 Universal Set of Gates ¡ A set of gates using which any combinational system can be built ¡ Example: {AND, OR, NOT} 10 More Examples of Universal Sets ¡ {AND, NOT} and {OR, NOT} 11 Another Universal Set: {NAND} 12 Mixed Logic Notation 13 Additional Complex Gate Structures in CMOS 14 Analysis of Gate Networks...
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M16_2_EEM16_F08_L06 - EEM16/CSM51A Logic Design of Digital...

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