M16_2_EEM16_F08_L07

# M16_2_EEM16_F08_L07 - EEM16/CSM51A Lecture#7 Ch5:...

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EEM16/CSM51A: Logic Design of Digital Systems Lecture #7 Ch 5: Design of Gate Networks Prof. Danijela Cabric Fall 2008

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Announcements ± HW#3 is posted on Eeweb ± HW#2 is due today 2
What is involved in creating a digital system? 3 Implementation Specification Synthesis (Design) Analysis

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Two Level Networks 4 Two types AND-OR network: Sum of Products OR-AND network: Product of Sums Inputs in complemented and uncomplemented forms
Two level networks with Different Costs for f(x2, x1, x0) = one set(3, 6, 7) 4 5

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Minimal Two Level Networks ± Goal: minimum area minimum # of transistors ± in real life, wires also cost area ± Algebraic definition: fewest # of literals and terms ± Each literal and term translates to a gate input, each of which translates to two transistors ± Inverters ignored 6
Minimal Expressions 7

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Graphical Representation of Switching Functions: Karnaugh Maps (or K Maps) ± 2 dimensional arrays of cells represent switching functions or expressions ± n variables 2 n cells ± Each cell represents a minterm ± cell i = assignment i ± minterms differing in one variable are ajacent ± adjacency condition any set of 2 r adjacent rows or columns: assignments differ in r variables ± Useful graphical aid in simplifying expressions 8
K Maps (n=1,2,3) 9

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K maps (n=4) 10
K maps (n=5) 11

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Representation of Switching Functions 12
K Maps 13

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Rectangles of 1 Cells and Sum of Products 14
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## This note was uploaded on 01/24/2012 for the course EE M16 taught by Professor Cabric during the Fall '08 term at UCLA.

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M16_2_EEM16_F08_L07 - EEM16/CSM51A Lecture#7 Ch5:...

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