M16_2_EEM16_F08_L09

M16_2_EEM16_F08_L09 - EEM16/CSM51A:...

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EEM16/CSM51A: Logic Design of Digital Systems Lecture #9 Ch 6: Design of Multilevel Networks Prof. Danijela Cabric Fall 2008
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Announcements ± HW#3 is due today ± HW#4 is posted on eeweb, due on Tue Nov 4 ± Midterm is next Tue Oct 28 in class ± Closed book ± You are allowed to bring one sheet of paper 8”x11” (two sided) with your own notes ± Special office hours on Monday Oct 27 10:00 11:00 2
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Agenda ± Quiz Review ± Transformations to satisfy constraints ± number of gate inputs ± network size ± network delay ± Design of networks with XOR and XNOR gates ± Design of networks with multiplexers (MUXes) 3
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Quiz (15 mins) 1. Check if this gate is universal: 4 10 1 0 00 1 0 01 1 0 1 0 x2 x1 x0 x3 2. a) Obtain minimal PoS and SoP for function F described with K map: XYX * Y 001 011 100 111 b) Implement function F using only NAND gates c) How many transistors do you need?
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Multi Level Networks ± Design more complex that for two level networks no standard form several requirements have to be met simultaneously (size, delay, fan in, fan out) multiple outputs 5
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This note was uploaded on 01/24/2012 for the course EE M16 taught by Professor Cabric during the Fall '08 term at UCLA.

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M16_2_EEM16_F08_L09 - EEM16/CSM51A:...

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