M16_2_EEM16_F08_L12

M16_2_EEM16_F08_L12 - EEM16/CSM51A:...

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EEM16/CSM51A: Logic Design of Digital Systems Lecture #12 Ch 8: Sequential Networks Prof. Danijela Cabric Fall 2008
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Announcements ± HW#5 is posted : Due Nov. 13 in class ± Make up lecture on Friday Nov. 21, time TBA ± In order to inform me about the time slot that works for you, please fill out the survey at: http://www.doodle.com/participation.html?pollId=wd5afm xdsiz2xset ± Available slots 2:00 4:00 PM, 4:00 6:00 PM, 6:00 8:00 PM 2
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Agenda ± Review: Canonical form of sequential networks ± Latches and edge triggered cells, D flip flop ± Set up time, hold time, and propagation delay ± Analysis and design of canonical networks ± SR, JK, and T flip flops 3
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Canonical Form of Sequential Networks 4
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Binary Implementation 5
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Storage element: Gated Latch – First Try 6 Level sensitive: when E = 1 then Q = D
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Remembering a Bit 7
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Gates with Feedback 8
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Problem with SR latch 9
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D Latch using SR Latch 10
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Implementation using Transmission Gates 11
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Limitations of Level Sensitive Latches 12
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Limitations of Level Sensitive Latches 13
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Solution: Edge Triggered Cell (D Flip flop) 14
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Implementing D Flip Flop: Master Slave Latches 15
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Practical D Flip Flop 16
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Timing Parameters of D Flip Flop 17
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Characteristics of a CMOS D Flip Flop (with only uncomplemented outputs) 18
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Timing Characteristics of Sequential Networks 19
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Network Hold Time 20
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Network Propagation Time 21
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This note was uploaded on 01/24/2012 for the course EE M16 taught by Professor Cabric during the Fall '08 term at UCLA.

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M16_2_EEM16_F08_L12 - EEM16/CSM51A:...

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