M16_2_EEM16_F08_L13

M16_2_EEM16_F08_L13 - EEM16/CSM51A:...

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EEM16/CSM51A: Logic Design of Digital Systems Lecture #13 Ch 8: Sequential Networks Prof. Danijela Cabric Fall 2008
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Announcements ± HW#6 is posted : Due Nov. 20 in class ± Make up lecture on Friday Nov. 21, 2:00 4:00 PM ± Place TBA on EEweb ± Lecture will be recorded and posted on EEweb 2
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Agenda ± Analysis and design of canonical networks ± SR, JK, and T flip flops ± Analysis of flip flop networks ± Design of flip flop networks; the excitation functions ± Special state assignments: one flip flop per state, and shifting register 3
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Design of Canonical Sequential Networks ± Transform the transition and output functions ± Specify a state register to hold the required number of states ± Design the required combinational network 4
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Example 5
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Example: Coding 6
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Example: State Transition and Output Functions 7
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Example: Implementation 8
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SR Flip Flop 9
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JK Flip Flop 10
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T (Toggle) Flip Flop 11
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Implementing one Flip flip Type with Another Example: T using JK 12
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Flip Flop Set and Reset Inputs 13
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Initial State 14
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This note was uploaded on 01/24/2012 for the course EE M16 taught by Professor Cabric during the Fall '08 term at UCLA.

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M16_2_EEM16_F08_L13 - EEM16/CSM51A:...

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