20085eeM16_2_Fall2008_Homework3

20085eeM16_2_Fall2008_Homework3 - are the most significant...

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UCLA Department of Electrical Engineering EEM16 Homework 3 Due October 23 rd , 2008 1. Exercise 4.4 2. Exercise 4.14 3. Exercise 5.3 4. Exercise 5.6 5. Two-bit Adder Design, Schematic and Simulation For this problem you will need to download and install Xilinx ISE as per the procedure given in the lecture slides and described by the TAs during the discussion sections. The software available from Xilinx’s web site runs on Windows and Linux, although I recommend that you run it under Windows. This is a large software package (in excess of 4 GB) and I suggest that you do it from a place where you have fast internet connectivity. a. Design a size-optimized two-level digital circuit that takes two 2-bit binary numbers X and Y i.e. <X1, X0> and <Y1, Y0>, where X1 and Y1
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Unformatted text preview: are the most significant bits of the two arguments, and X0 and Y0 are the least significant bits. The output is a bit vector Z with enough bits to represent all possible values that the sum of X and Y can take. b. Enter your circuit as a schematic in Xilinx ISE using gates from the set {NOT, AND, OR, NAND, NOR}. Submit a printout of the schematic that you draw in Xilinx ISE. c. Show that you circuit works correctly by simulating it in Xilinx ISE for all possible input values of X and Y. Arrange for the inputs to change at time instants that are multiples of 100 ns. Print out the results of simulation produced by the tool to demonstrate that you indeed were able to simulate successfully....
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This note was uploaded on 01/24/2012 for the course EE M16 taught by Professor Cabric during the Fall '08 term at UCLA.

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