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20085eeM16_2_Homework5 - consisting of both the input...

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UCLA Department of Electrical Engineering EEM16 Homework 5 Due November 13 th , 2008 1. Exercise 7.7 2. Exercise 7.17 3. Exercise 7.23. Implement this system in the Xilinx ISE toolchain using VHDL. Simulate your system using the given input sequence and show the simulation result in Xilinx. Turn in printouts of your VHDL code and your simulation results
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Unformatted text preview: consisting of both the input vector and the resulting output. Hint: Remember to make use of the VHDL examples at the end of each chapter in your book and the power point presentation on VHDL that is posted on EEweb. Also, go through the Xilinx Quick Start tutorial (Help>Tutorials>ISE Quick Start) on VHDL and simulation....
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