20085eeM16_2_Homework5_soln

# 20085eeM16_2_Homework5_soln - UCLA Department of Electrical...

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UCLA Department of Electrical Engineering EEM16 Homework 5 Due November 13 th , 2008 1. Exercise 7.7 There are sixteen possible states. To obtain the state diagram, we first obtain the state table, by an evaluation of the expressions. To simplify the notation, we label the states with an integer 0 j 15 whose binary representation is the bit-vector (s 3 , s 2 , s 1 , s 0 ). The state table is

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State diagram for Exercise 7.7
2. Exercise 7.17 Based on the outputs for each state we get the first partition P 1 = (A, C, G, H)(B, D, E)(F) To obtain P 2 , we determine the class of P 1 to which the successors of the states belong.

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3. Exercise 7.23. Implement this system in the Xilinx ISE toolchain using VHDL. Simulate your system using the given input sequence and show the simulation result in Xilinx. Turn in printouts of your VHDL code and your simulation results consisting of both the input vector and the resulting output.
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20085eeM16_2_Homework5_soln - UCLA Department of Electrical...

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