20085eeM16_2_Homework6

20085eeM16_2_Homework6 - Apply the necessary logic to the...

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UCLA Department of Electrical Engineering EEM16 Homework 6 Due November 20 th , 2008 1. Design a counter with one control input. When the input is high, the counter should sequence through three states: 10, 01, 11 and repeat. When the input is low the counter should sequence through the same states in the opposite order 11, 01, 10 and repeat. a) Draw the state diagram and state transition table b) Implement the counter using D flip flops and whatever gates you like. c) Is your counter self-starting with the input either high or low? 2. Exercise 8.13 Note: Assume you must always input 4 digits at a time in sequence. For example, let’s say you enter in 1 digit correctly. Then you make a mistake when entering the 2 nd digit. You must enter the 3 rd and 4 th digit as well. You cannot “reset” or start over after only entering 2 digits. 3. Show how to implement a D flip-flop starting with a J-K flip-flop.
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Unformatted text preview: Apply the necessary logic to the input of a J-K flip-flop such that it behaves like a D flip-flop. 4. Show how to implement a T flip-flop starting with a D flip-flop. Apply the necessary logic to the input of a D flip-flop such that it behaves like a T flip-flop. 5. a) Using only JK Flip-flops and NAND gates from the table below, design a sequential network that outputs 1 if at least 4 of the last 7 input bits were 1. Otherwise the output is 0. You should optimize your circuit to minimize the numbers of flip-flops and gates used. You must show details of how you designed and optimized the sequential network to get any credit. b) What is the fastest clock frequency that your circuit can operate at? Use data from tables below. 6. Obtain the state diagram of the sequential network show below....
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This note was uploaded on 01/24/2012 for the course EE M16 taught by Professor Cabric during the Fall '08 term at UCLA.

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20085eeM16_2_Homework6 - Apply the necessary logic to the...

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