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Unformatted text preview: Apply the necessary logic to the input of a J-K flip-flop such that it behaves like a D flip-flop. 4. Show how to implement a T flip-flop starting with a D flip-flop. Apply the necessary logic to the input of a D flip-flop such that it behaves like a T flip-flop. 5. a) Using only JK Flip-flops and NAND gates from the table below, design a sequential network that outputs 1 if at least 4 of the last 7 input bits were 1. Otherwise the output is 0. You should optimize your circuit to minimize the numbers of flip-flops and gates used. You must show details of how you designed and optimized the sequential network to get any credit. b) What is the fastest clock frequency that your circuit can operate at? Use data from tables below. 6. Obtain the state diagram of the sequential network show below....
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This note was uploaded on 01/24/2012 for the course EE M16 taught by Professor Cabric during the Fall '08 term at UCLA.
- Fall '08
- Electrical Engineering