M16_2_Discussion_7

M16_2_Discussion_7 - EEM16 Fall 2008 11/14/2008 Discussion...

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EEM16 Fall 2008 11/14/2008 Discussion 7: Problems and Solutions 1. Exercise 8.3 (a) There are no race conditions because of overlapping nature of the two clocks. This assures that in each clock cycle only one state change occurs. (b) The state can be described by two components s1 (stored in register 1) and s2 (stored in register 2). Each component changes in alternate clock cycles. In this case each register stores part of the state and the number of potential states is 2 2n , but all these states cannot be utilized in general. (c) Split the combinational network, reducing the propagation delay between latches, as shown in Figure 8.1. Observe that one more latch is used in this case. 2. Design of State Machines : A finite state machine has one input and one output. The output becomes 1 and remains 1 thereafter when at least two 0s and at least two 1s have occurred as inputs, in any order after reset. Draw a state diagram of this FSM as a Moore machine. Solution: The inputs can occur “in any order”, so we don’t need to be concerned about the particular sequence of the inputs. Since this problem asks for a Moore machine, we need to define states that have an output associated with that state.
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M16_2_Discussion_7 - EEM16 Fall 2008 11/14/2008 Discussion...

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