M16_2_EEM16_F08_L01

M16_2_EEM16_F08_L01 - EEM16/CSM51A: Logic Design of Digital...

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EEM16/CSM51A: Logic Design of Digital Systems Lecture #1 Introduction Prof. Danijela Cabric Fall 2008
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Course Staff ± Instructor: Danijela Cabric ± Assistant Professor in EE Department ± Email: danijela@ee.ucla.edu ± Office: 56 147C Eng. IV ± Teaching Assistant: Diane Budzik ± Graduate Student in EE Department ± Email: dbudzik@ee.ucla.edu ± Teaching Assistant: Rahul Balani ± Graduate Student in EE Department ± Email: rahulbalani@gmail.com 2
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Schedule Problem Sets Due * Discussion sessions cover identical material Mon Tue Wed Thu Fri Lecture CS50 WGYOUNG Lecture DISC 2B&2D 5252 Boelter 8 9 10 11 12 1 2 3 4 5 6 OH-Prof 56-147C Eng-4 TA mtg OH - Diane 53-125 Eng-4 EEM16 WEEKLY SCHEDULE OH - Rahul 53-125 Eng-4 OH-Prof 56-147C Eng-4 CS50 WGYOUNG DISC 2A 5252 Boelter DISC 2C 5252 Boelter 6229 MS 3
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Grading ± Homeworks (28%) ± 7 homeworks (both theoretical and small simulation/design projects) ± Due on Thursday at the end of the lecture ± No late homeworks accepted ± Quizzes (6%) ± 3 short (~20 mins) quizzes ± Not scheduled, assigned at random ± Midterm (25%) ± Week 6, October 28 ± In class, closed book ± Final (40%) ± December 12 ± In class, closed book, cumulative ± Course Survey on EEWEB (1%) 4
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What is this course about? ± Description and design of digital systems such as computers ± Formal basis in switching algebra ± Implementation aspects: modules and network of modules ± Implementation of algorithms in hardware ± Course emphasis: concepts, methods, and design ± Follow on courses ± Digital design lab (EEM116L/CSM152A) ± Computer architecture (EEM116C/CSM151B) ± Digital design project (EEM116D/CSM152B) ± Digital circuits (EE115C) 5
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Textbook ± Introduction to Digital Systems (Hardcover) by Miloš Ercegovac, Tomás Lang, Jaime H. Moreno ± John Wiley & Sons, Inc. ± ISBN 10: 0471527998 ± ISBN 13: 978 0471527992 ± Available at ± ASUCLA ± On line stores such as Amazon.com ± Note: lecture slides will have material from other sources as well 6
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Course Web Site ± Hosted on EEWEB https://www.eeweb.ee.ucla.edu/classinfo.php? /eeM16/2/fall/08 ± Login using your BOL account id and password ± Copies of handouts, homeworks, exams etc. ± Password protected parts of web site user=visitorM16, password=flipflop 7
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Syllabus (posted on EEweb) 8 Week Date Day Lecture Due Reading 1 Sep 25 Thu Introduction about Digital Systems Ch 1 2 Sep 30 Tue Combinational systems: Specification, Data representation, Switching functions Ch. 2.1 2.4.1 Appendix A Oct 2 Thu Combinational systems: Switching expressions, Karnaugh maps Ch. 2.4.2, 2.5, 2.6 3 Oct 7 Tue Combinational ICs: CMOS switches and gates and their characteristics; Buses and three state drivers; Design styles Ch. 3 Oct 9 Thu Gate networks: Description and analysis HW 1 Ch. 4 4 Oct 14 Tue Gate networks: Design of two level & minimal networks; PLAs and PALs; Multilevel networks; Ch. 5, 6 Oct 16 Thu Sequential systems: Specifications, states, time behavior, reduction of state set HW 2 Ch. 7 5 Oct 21 Tue Sequential systems: Implementation, canonical networks, analysis and synthesis, sequential networks with flip flops Ch. 8 Oct 23 Thu
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M16_2_EEM16_F08_L01 - EEM16/CSM51A: Logic Design of Digital...

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