M16_2_discussion3_soln

M16_2_discussion3_soln - UCLA page 7 of 15 ‘ ' Spring...

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Unformatted text preview: UCLA page 7 of 15 ‘ ' Spring 2008 Due Date: Tue April 29, 2008 @ 1 PM I .[OII'I 3! O] " Problem #2 [2*10=20]: Miscellaneous Please write our answer in the space provided after each part of this question. a) Is the gate 63 , where A (9 B = A - B’ universal? You may use constants C and 1 if needed. Prove your answer. Ami—“Avg” A?) warm ANSWER: ~ - = ' 4 t 'vem/ ANOJUIZps/UT :1 A a”; 0‘ bf“ K , I {dim [Widogfx A wow/M} yJfi A2] Eff? Nu "’ - o NANO «.w 5mm “5'”? °““/ 9 NOT ,, ~ij (in Qxffli'fl AND/0R) NOT :1 a 0/ AW) - UCLA page 8 of 1 5 II.) FI‘IIQVAVLO}: H Spring 2008 Due Date: Tue April 29, 2008 @ 1 PM c) Write a switching expression for the circuit in part (b) ANSWER XIV/,2, ‘* X7— . ‘ (x/\//+>()1 ‘Al‘l‘ivjyt‘gdlyfiy {XW'JL JamyD/\{,“,,qh )(2 “r yl'Z. d) Draw an equivalent circuit for the circuit in part (b) using fewer NAN D gates (and no gates of any other type). The NAN D gates may have any # of inputs. W ANSWER Ly xz + y’z) 2x75) X >1 4 “ED >5) 7’ C) Show that the following circuit is combinational even though the circuit has a physical loop. if :i 19 : {z X \ 1, = my + LU”); : (£(0‘gl ‘5 S (R, *ZIIJ : (May +5: *5/24, : (1(C‘S’flfi. ~59) - UCLA page 9 of 15 - - I I 3‘1".) : Spring 20 08 Due Date: Tue April 29, 2008 @ 1 PM ANSWER: f) A logic famin uses the following ranges of voltages to represent high and low values: l-llGl-i - 2.2V to 3 V. and LOW - 0.0 V to 0.8 V. Consider a circuit with two inputs x and y, and an output 7.. and whose behavior for certain input voltages was as below: What type of logic gate does the circuit implement for positive and negative logic respectiwly? ANSWER: Pam w, - UCLA page 10 of 1 5 I 0 I] QAKOII. 39""9 2°08 Due Date: Tue April 29, 2008 @ 1 PM g) Write the switching expression corresponding to the logic function that is implemented by the following CMOS circuit. TVim f-\ O (MCDY eco A F: ElfAGCD)’ Nofl 3L§K : [E WAGCDD/ AN SWER: h) Implement using transmission gates the same logic function as is implemented by the CMOS circuit in part (g). As- sume that you already have A, B, C, D, and E available in both polarities (i.e. In both uncomplemented and com- plemented forms). | ~ .~ , ANSWER: 4NNM'QM SAL k ‘ CM“ mm c “WWW” y X £33] \l #1) k 0 I Z LT njwi‘ltk l H on )( \sdwr “0A. a“ 7— [ DOF‘ZJIYLNJflHSJMJA silk {" ,Q'ét 1W M‘lPrX/J p‘rf Mm HY kW] $wl' Mil P ‘3 5w“ «WM» - UCLA page11 of 15 IOJI'IIa'Moli: Spring zoos Due Date: Tue April 29, 2008 @ 1 PM i) Determine the output load of gate I in the following circuit. L: “i H“ AN SWER: j) How many additional gates with load factor of I can be connected to the output of gate 6 in the circuit shown for part (i)? ANSWER: H 9 CM ...
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M16_2_discussion3_soln - UCLA page 7 of 15 ‘ ' Spring...

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