# HW3 - has to make a transition in order to achieve this...

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EECS 170D Homework #3 Due in class Thursday November 1 st , 2007 Unless otherwise stated, the following parameters are assumed for the MOS Transistors: Technology : 0.25 um V to (V) Gamma V 1/2 V Dsat (V) K’(A/V 2 ) Lambda(V -1 ) NMOS 0.43 0.4 0.63 115x10 -6 0.06 PMOS -0.4 -0.4 -1 -30X10 -6 -0.1 Question1: Static CMOS Consider the circuit shown above: a. What is the logic function implemented by the CMOS transistor network? Size the NMOS and the PMOS devices so that the output resistance is the same as that of an inverter with an NMOS W/L=4 and PMOS W/L=8. EECS170D Fall 07

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EECS 170D Homework #3 Due in class Thursday November 1 st , 2007 b. What are the input patterns that give the worst case tpHL and tpLH. State clearly what are the initial input patterns and which input(s)
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Unformatted text preview: has to make a transition in order to achieve this maximum propagation delay. Consider the effect of the capacitances at the internal nodes. (provide only a qualitative discussion, without going into exact equations) Question 2: Pass transistor Logic a. Determine the truth table for the circuit. What logic function does it implement? (Assume the PMOS device is weak) b. Assuming 0 and 2.5V inputs, size the PMOS transistor to achieve a V OL of 0.3V. c. If the PMOS were removed, would the circuit still function correctly? Does the PMOS transistor serve any useful purpose? EECS170D Fall 07...
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