This preview shows pages 1–2. Sign up to view the full content.
This preview has intentionally blurred sections. Sign up to view the full version.
View Full Document
Unformatted text preview: d. Determine a closed form expression for the power consumption in the circuit. Consider only gate capacitances in your analysis. What is the power consumption for a supply voltage of 2.5V and an activity factor of 1? In 1 ? ? Out 1 is the minimum sized inverter Ci CL Ci = 10fF CL = 20pF Added Buffer Stage EECS 170D Homework #5 Due in class Tuesday November 27 th , 2007 Problem #2 An NMOS transistor is used to charge a large capacitor, as shown in the figure below. a. Determine the tpLH of this circuit, assuming an ideal step from 0 to 2.5V at the input node. 2 f = .6V b. Assume that a resistor RS of 5 k is used to discharge the capacitance to ground. Determine tpHL . c. The NMOS transistor is replaced by a PMOS device, sized so that kp is equal to the kn of the original NMOS. Will the resulting structure be faster? Explain why or why not. In Out 2.5/.25 M1 VDD = 2.5V CL = 5pF...
View
Full
Document
This note was uploaded on 01/24/2012 for the course EECS 170d taught by Professor Staff during the Fall '08 term at UC Irvine.
 Fall '08
 staff
 Transistor

Click to edit the document details