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Unformatted text preview: d. Determine a closed form expression for the power consumption in the circuit. Consider only gate capacitances in your analysis. What is the power consumption for a supply voltage of 2.5V and an activity factor of 1? In 1 ? ? Out ‘1’ is the minimum sized inverter Ci CL Ci = 10fF CL = 20pF Added Buffer Stage EECS 170D Homework #5 Due in class Tuesday November 27 th , 2007 Problem #2 An NMOS transistor is used to charge a large capacitor, as shown in the figure below. a. Determine the tpLH of this circuit, assuming an ideal step from 0 to 2.5V at the input node. 2 φ f = .6V b. Assume that a resistor RS of 5 kΩ is used to discharge the capacitance to ground. Determine tpHL . c. The NMOS transistor is replaced by a PMOS device, sized so that kp is equal to the kn of the original NMOS. Will the resulting structure be faster? Explain why or why not. In Out 2.5/.25 M1 VDD = 2.5V CL = 5pF...
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 Fall '08
 staff
 Transistor, propagation delay, EECS 170D Homework, VTO

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