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hw5_170

# hw5_170 - d Determine a closed form expression for the...

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EECS 170D Homework #5 Due in class Tuesday November 27 th , 2007 Unless otherwise stated, the following parameters are assumed for the MOS Transistors: Technology : 0.25 um V to (V) Gamma V 1/2 V Dsat (V) K’(A/V 2 ) Lambda(V -1 ) NMOS 0.43 0.4 0.63 115x10 -6 0.06 PMOS -0.4 -0.4 -1 -30X10 -6 -0.1 Problem #1: Sizing a chain of inverters. a. In order to drive a large capacitance (CL = 20 pF) from a minimum size gate (with input capacitance Ci = 10fF), you decide to introduce a two-staged buffer as shown below. Assume that the propagation delay of a minimum size inverter is 70 ps. Also assume that the input capacitance of a gate is proportional to its size. Determine the sizing of the two additional buffer stages that will minimize the propagation delay. b. If you could add any number of stages to achieve the minimum delay, how many stages would you insert? What is the propagation delay in this case? c. Describe the advantages and disadvantages of the methods shown in (a) and (b).

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Unformatted text preview: d. Determine a closed form expression for the power consumption in the circuit. Consider only gate capacitances in your analysis. What is the power consumption for a supply voltage of 2.5V and an activity factor of 1? In 1 ? ? Out ‘1’ is the minimum sized inverter Ci CL Ci = 10fF CL = 20pF Added Buffer Stage EECS 170D Homework #5 Due in class Tuesday November 27 th , 2007 Problem #2 An NMOS transistor is used to charge a large capacitor, as shown in the figure below. a. Determine the tpLH of this circuit, assuming an ideal step from 0 to 2.5V at the input node. 2 φ f = .6V b. Assume that a resistor RS of 5 kΩ is used to discharge the capacitance to ground. Determine tpHL . c. The NMOS transistor is replaced by a PMOS device, sized so that kp is equal to the kn of the original NMOS. Will the resulting structure be faster? Explain why or why not. In Out 2.5/.25 M1 VDD = 2.5V CL = 5pF...
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hw5_170 - d Determine a closed form expression for the...

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