EECS 170D Homework #6
Due in class Tuesday December 4
th
, 2007
Solution to Problem1:
Solution to Problem 2:
A dynamic logic gate is shown above. During the precharge phase (
φ
= 0) output F
is charged to VDD and it is given that A = B = C = D = 0V. During the evaluate
phase (
φ
=0), any of these inputs may or may not change.
a) What is the worstcase combination of input transitions in terms of charge
sharing? That is, what input combination will corrupt F the most when the output is
supposed to remain high?
Solution:
The worst case is when A and C both transition from 0 to 1 and parasitic
capacitances at both internal nodes share charge from the output node.
b) For the worstcase identified in part (a), what is the final voltage at node F? Use
VDD = 1.5V, NMOS model VTH0 = 0.5V,
γ
= 0.4V, 2
φ
F = 0.6V, assume that Cdb
=Csb = 1fF for all transistors and ignore gate capacitance.
Solution:
Assume that F doesn’t change much, so that transistors A and C remain in
saturation until they cut off when the internal nodes reach VDDVTH. In this case
the internal nodes are charged to some voltage Vx determined by:
EECS170D
Fall 07
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 Gate, Logic gate, Inductor, EECS 170D Homework

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