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Unformatted text preview: a) What is the worst-case combination of input transitions in terms of charge sharing? That is, what input combination will corrupt F the most when the output is supposed to remain high? b) For the worst-case identified in part (a), what is the final voltage at node F? Use VDD = 1.5V, NMOS model VTH0 = 0.5V, γ = 0.4V, 2 φ F = 0.6V, assume that Cdb =Csb = 1fF for all transistors and ignore gate capacitance. c) In addition to the charge sharing calculated in part (b), now assume that there is also a constant leakage current of 2nA discharging node F to ground. What is that minimum clock speed that this gate can operate at if the next gate has VIH = 1.0V? Assume that clock φ is high and low for equal periods of time....
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- Fall '08
- Transistor, Logic gate, EECS 170D Homework