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HW6_v1 - a What is the worst-case combination of input...

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EECS 170D Homework #6 Due in class Tuesday December 4 th , 2007 EECS170D Fall 07 Unless otherwise stated, the following parameters are assumed for the MOS Transistors: Technology : 0.25 um V to (V) Gamma V 1/2 V Dsat (V) K’(A/V 2 ) Lambda(V -1 ) NMOS 0.43 0.4 0.63 115x10 -6 0.06 PMOS -0.4 -0.4 -1 -30X10 -6 -0.1 Problem 1: Sketch the waveforms at x , y , and z for the given inputs. You may approximate the time scale, but be sure to compute the voltage levels. Assume that VT = 0.5 V when body effect is a factor. VDD=2.5V.
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EECS 170D Homework #6 Due in class Tuesday December 4 th , 2007 EECS170D Fall 07 Problem 2: A dynamic logic gate is shown above. During the pre-charge phase ( φ = 0) output F is charged to VDD and it is given that A = B = C = D = 0V. During the evaluate phase ( φ =0), any of these inputs may or may not change.
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Unformatted text preview: a) What is the worst-case combination of input transitions in terms of charge sharing? That is, what input combination will corrupt F the most when the output is supposed to remain high? b) For the worst-case identified in part (a), what is the final voltage at node F? Use VDD = 1.5V, NMOS model VTH0 = 0.5V, γ = 0.4V, 2 φ F = 0.6V, assume that Cdb =Csb = 1fF for all transistors and ignore gate capacitance. c) In addition to the charge sharing calculated in part (b), now assume that there is also a constant leakage current of 2nA discharging node F to ground. What is that minimum clock speed that this gate can operate at if the next gate has VIH = 1.0V? Assume that clock φ is high and low for equal periods of time....
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HW6_v1 - a What is the worst-case combination of input...

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